E-FET Composite Barrier Layer Gate Dielectric Recess
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Solution Overview
Problem
Enhancement mode field-effect transistors (E-FETs) face a trade-off between threshold voltage and static on resistance, where increasing threshold voltage increases static on resistance, and decreasing it decreases threshold voltage, making it challenging to achieve high performance.
Innovation Solution
A composite barrier layer with a lower and upper barrier layer of different polarizations, along with a gate opening that reduces electron density under the gate, allowing for high threshold voltage while maintaining low static on resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the threshold voltage is increased, then the static on resistance increases, but if the threshold voltage is decreased, then the static on resistance decreases
Solution Approach 1:
The barrier layer is divided into multiple segments with different compositions and polarizations. The first barrier layer has a first polarization and the second barrier layer has a second polarization different from the first, allowing independent optimization of threshold voltage and static on resistance characteristics in different regions of the device
Solution Approach 2:
Different regions of the barrier layer are assigned different local properties through the use of barrier layers with different polarizations. This allows the device to have high threshold voltage in regions where needed while maintaining low static on resistance in other regions, resolving the trade-off between these two parameters
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the dependence between threshold voltage and static on resistance, enabling E-FETs to have high threshold voltage with low static on resistance, improving performance.
Implementation Method 1
The composite barrier layer comprises a lower barrier layer and an upper barrier layer with different polarizations
Implementation Method 2
The gate dielectric layer is a group III nitride with a p-type doping, such that the gate dielectric layer depletes the 2-DEG immediately under the gate dielectric layer
Data Source
AI summary
An enhancement mode field-effect transistor (E-FET) for high static performance is provided. A composite barrier layer comprises a lower barrier layer and an upper barrier layer. The upper barrier layer is arranged over the lower barrier layer and has a different polarization than the lower barrier layer. Further, the composite barrier layer comprises a gate opening. A channel layer is arranged under the composite barrier layer, such that a heterojunction is defined at an interface between the channel layer and the composite barrier layer. A gate dielectric layer is arranged over the composite barrier layer and within the gate opening. A gate electrode is arranged over the gate dielectric layer. A method for manufacturing the E-FET is also provided.