eFuse Cell Layout With Shared Transistor for Lower Program Resistance

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Solution Overview

Problem

Existing eFuse cells in integrated circuits face challenges with increased resistance in program paths due to longer lengths, leading to poor performance.

Innovation Solution

The eFuse cell design incorporates a configuration where two fuses share a transistor (1T2R) to reduce the layout size and resistance in the program path, enhancing performance by optimizing the layout structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the program path length is increased to accommodate more fuses, then the storage capacity is improved, but the resistance increases leading to poor performance

Engineering Contradiction:

Improvestorage capacityVSAvoidperformance

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent combines multiple fuse elements into a shared program path structure where fuses are arranged in parallel branches rather than sequential series. This merging approach allows multiple fuses to be controlled through a common path, increasing storage capacity without proportionally increasing the total path length and resistance.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from a one-dimensional sequential fuse arrangement to a two-dimensional layout where fuses are organized in parallel branches. This dimensional change allows more fuses to be accommodated within a compact area while maintaining shorter individual path lengths, thereby reducing resistance while increasing storage capacity.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Area of stationary object

If the layout size is reduced to increase density, then the area efficiency is improved, but the program path length increases leading to higher resistance

Engineering Contradiction:

Improvelayout sizeVSAvoidresistance

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The patent merges multiple fuse elements into shared program path branches, allowing a higher density of fuses within a reduced layout area. The shared path structure ensures that the effective program path length remains short even as more fuses are packed into the same area, maintaining low resistance while achieving compact design.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent creates a universal program path structure that serves multiple fuse elements simultaneously. The shared control lines and common path segments perform the function of programming multiple fuses without requiring separate dedicated paths for each fuse, thereby reducing overall layout size while maintaining performance.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250364066A1Integrated circuit including efuse cell

Publication Date: 2025.11.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

An integrated circuit includes a transistor, a first fuse element and a second fuse element. The transistor is formed in a first conductive layer. The first fuse element is formed in a second conductive layer and coupled between the transistor and a first data line. The second fuse element is formed in the second conductive layer and coupled between the transistor and a second data line. The first fuse element and the second fuse element are disposed at a same side of the transistor.