Dielectric Fin eFuse Cells for Dense OTP Memory Integration
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Solution Overview
Problem
The challenge of integrating one-time-programmable (OTP) memory devices, such as efuse devices, into advanced integrated circuits is exacerbated by the mismatch in size reduction rates between efuse components and transistor features, leading to increased real estate requirements that hinder integration.
Innovation Solution
The efuse cells are designed with a fork configuration that includes a dielectric fin structure interposed between nanostructures acting as channels for sub-transistors, reducing the area required for each efuse cell and allowing more cells to be integrated within a given space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If efuse cells are designed with traditional configurations, then the device functionality is maintained, but the area occupied by each efuse cell increases, reducing integration density
Solution Approach 1:
The patent implements a fork configuration where one efuse cell shares common structures (gate electrode, interconnects, contacts) between multiple sub-transistors, creating a nested arrangement that reduces the total area. The dielectric fin structure enables two sub-transistors to be nested within a shared gate structure, effectively halving the area requirement per functional unit.
Solution Approach 2:
The patent merges multiple transistor functions into a single efuse cell by combining two sub-transistors that share common gate electrodes, interconnect structures, and contact regions. This merging of structures allows the efuse cell to maintain full functionality while occupying reduced area on the semiconductor substrate.
2Productivity
If efuse device size is reduced to match transistor feature scaling, then integration efficiency improves, but traditional efuse structures cannot achieve sufficient size reduction
Solution Approach 1:
The patent transitions from planar transistor structures to three-dimensional vertical structures by introducing dielectric fin structures that extend vertically from the substrate. This dimensional change allows multiple channel structures to be stacked vertically, achieving area reduction that outpaces conventional two-dimensional scaling and enables efuse devices to keep pace with transistor feature size reduction.
Solution Approach 2:
The patent segments the efuse cell into multiple sub-transistors (first and second sub-transistors) that share common structures. This segmentation allows the cell to be divided into functional units that can be efficiently packed and shared, reducing the overall area requirement while maintaining the necessary functionality for one-time programmable memory operations.
3Quantity of substance
If more efuse cells are integrated into a given space, then memory capacity increases, but the area per cell must be reduced
Solution Approach 1:
The patent creates universal structures that serve multiple functions: the shared gate electrode serves both sub-transistors, the common interconnects provide multiple electrical connections, and the dielectric fin structure provides both isolation and structural support. This multi-functionality allows a higher density of efuse cells to be packed into the same area without compromising individual cell functionality.
Data Source
AI summary
A semiconductor device includes a plurality of first nanostructures extending along a first lateral direction. The semiconductor device includes a first epitaxial structure and second epitaxial structure respectively coupled to ends of each of the plurality of first nanostructures along the first lateral direction. The semiconductor device includes a dielectric fin structure disposed immediately next to a sidewall of each of the plurality of first nanostructures facing a second lateral direction perpendicular to the first lateral direction. The semiconductor device includes a first gate structure wrapping around each of the plurality of first nanostructures except for the sidewalls of the first nanostructures. The semiconductor device includes a metal structure disposed above the first gate structure and coupled to one of the first or second epitaxial structure.