eFuse Cell Backside Power Rail Layout for Low-Resistance Programming
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Solution Overview
Problem
Existing eFuse devices in integrated circuits face challenges due to high resistance in vias transmitting power from the backside to the frontside, making it difficult to program IC components effectively.
Innovation Solution
The eFuse cells are coupled to backside power rails through via structures, reducing resistance and power dissipation by providing supply voltage from the backside, and incorporating additional via structures to improve conduction paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power is transmitted from the backside to the frontside through vias, then the eFuse cells can be programmed, but the via resistance is high making programming difficult
Solution Approach 1:
The patent transitions from traditional frontside power delivery to backside power delivery through via structures, utilizing the vertical dimension to route power rails from the backside of the substrate to the eFuse cells on the frontside. This dimensional change allows power to be delivered from an alternative direction, enabling the use of backside vias and tap regions to reduce the resistance in the power transmission path.
Solution Approach 2:
The patent introduces intermediary structures including backside vias and tap regions that serve as intermediate connection points between the backside power rails and the frontside eFuse cells. These intermediary elements provide additional conduction paths and reduce the overall resistance by distributing the power delivery through multiple intermediate connection points rather than relying on a single direct via path.
2Reliability
If additional via structures are incorporated, then conduction paths are improved, but device complexity increases
Solution Approach 1:
The patent merges multiple functions into the backside power rail structure, combining power delivery, signal routing, and structural support into a single integrated system. The backside power rails serve both as power transmission paths and as structural elements that can be shared across multiple eFuse cells, reducing the need for separate via structures for each cell and thereby lowering overall device complexity while maintaining improved conduction paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances programming efficiency and flexibility in IC design by reducing resistance and improving manufacturing ease.
Implementation Method 1
The eFuse cells are coupled to backside power rails through via structures, reducing resistance and power dissipation by providing supply voltage from the backside
Data Source
AI summary
A semiconductor device includes a semiconductor substrate having a first side and a second side opposite the first side. The semiconductor device further includes a first active region disposed on the first side of the semiconductor substrate. The semiconductor device further includes a metallization layer disposed on the second side of the semiconductor substrate and including a metal line. The semiconductor device further includes a transistor disposed in the first active region and including a source region and a drain region. The semiconductor device further includes a via extending through the semiconductor substrate and the first active region. In some aspects, the via couples the metal line to the source region or the drain region of the transistor.