EIC-PIC Optical Engine Assembly Using Hybrid Bonded Wafer Stacks
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Solution Overview
Problem
Existing assembly methods for integrating electronic integrated circuits (EIC) and photonic integrated circuits (PIC) face challenges in advanced technology nodes, such as 7 nm and below, due to issues like BEOL reliability, die warpage, and incompatibility with via last processes, leading to potential cracking and increased die size.
Innovation Solution
A method involving hybrid face-to-back bonding of a short-loop wafer to a thin CMOS wafer, forming a two-substrate stack, which is then thinned and processed with TSVs using a thick metal layer as an etch stop, enhancing wafer handling and stability for 3D stacking with PICs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If through-silicon via (TSV) integration is performed on thin silicon substrates, then device density and performance are improved, but wafer warping and cracking occur
Solution Approach 1:
The patent divides the substrate processing into multiple stages: first forming a support structure, then performing TSV integration, and finally removing the support. This segmentation allows TSV processing to be performed on a supported substrate rather than a thin free-standing substrate, preventing warping and cracking while maintaining manufacturing precision
Solution Approach 2:
The patent introduces a removable support structure as an intermediary element during the TSV integration process. This support acts as a mediator that provides mechanical strength to the thin substrate during critical processing steps, enabling precise TSV formation without causing substrate failure
2Volume of moving object
If silicon substrate thickness is reduced for advanced technology nodes, then device density is improved, but compatibility with existing assembly flows deteriorates
Solution Approach 1:
The patent segments the assembly process into distinct phases: substrate preparation with support structure, TSV formation, support removal, and final assembly. This segmentation allows thin substrates to be processed using modified but compatible assembly flows, maintaining adaptability while enabling advanced technology nodes
Solution Approach 2:
The patent performs preliminary actions by forming the support structure before TSV integration and removing it after TSV formation. This preliminary support enables thin substrate processing with existing assembly equipment, maintaining compatibility while achieving reduced substrate thickness for advanced nodes
3Length of moving object
If deep trenches or TSVs are formed in thin substrates, then interconnect length is reduced, but wafer warping and cracking increase
Solution Approach 1:
The patent provides beforehand cushioning by forming a support structure prior to deep trench or TSV formation. This support cushions the thin substrate against the mechanical stresses of deep etching, enabling short interconnect formation without causing warping or cracking
Solution Approach 2:
The patent segments the deep trench formation process into stages with support structure present during critical etching steps, then removes the support after trench formation. This allows achievement of short interconnect lengths while maintaining structural stability through staged processing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach strengthens the EIC-PIC stack, reducing the risk of cracking and warpage, enabling reliable assembly and integration into optical engines with improved mechanical stability and reduced thickness.
Implementation Method 1
an etch stop is achieved by utilizing a thick metal layer on the front side of the SL wafer
Implementation Method 2
hybrid front-to-back bonding of a short-loop (SL) wafer to a thin CMOS wafer
Data Source
AI summary
The current invention offers a method for preparing an electronic integrated circuit (EIC) for the assembly of an optical engine. The method involves stacking a CMOS-based EIC wafer onto a short loop/interposer wafer through face-to-back bonding. This stacked configuration serves as a carrier for the thin CMOS wafers. Subsequently, the stacked wafers are thinned down to the desired height and undergo a via last process. In this process, the thick metal layer from the short loop/interposer wafer acts as an etch stop. The stacked EIC wafers can then be diced and attached to a photonic integrated circuit (PIC) wafer, resulting in the formation of an optical engine.