Elastic Bonding Head for Flattening Warped Semiconductor Chips

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Solution Overview

Problem

Miniaturized and thinned semiconductor chips are prone to warpage due to external stress and heat, which can cause damage and affect electrical connections during bonding processes.

Innovation Solution

A method involving the application of varying forces through elastic members to flatten semiconductor chips before bonding, using a bonding device with a housing, elastic members, and a heat generator to apply these forces uniformly and reduce internal stress.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If semiconductor chips are miniaturized and thinned to achieve higher performance and density, then productivity and integration are improved, but the chips become more susceptible to warpage under external stress and heat

Engineering Contradiction:
Improvesemiconductor package manufacturing efficiencyVSAvoidchip warpage resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by flattening the semiconductor chip before bonding through a pressing process. The pressing device applies force to the chip surface to correct warpage in advance, ensuring the chip is flat before subsequent bonding operations. This prevents warpage-related failures during bonding while maintaining miniaturization benefits.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If uniform force is applied to flatten the semiconductor chip, then manufacturing precision is improved, but the complexity of the bonding device increases

Engineering Contradiction:
Improvechip flatnessVSAvoidbonding device structure
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The pressing device is segmented into multiple independent pressing elements that can be arranged in a matrix pattern. Each element can apply force independently to different regions of the chip. This segmentation allows uniform force distribution across the chip surface while keeping each individual pressing element simple in structure, resolving the contradiction between precision and complexity.

Inventive Principle:
Principle #1Segmentation

3Reliability

If multiple forces are applied to different points of the chip through elastic members, then warpage is reduced, but the device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improvewarpage preventionVSAvoidelastic members configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent utilizes parameter changes by employing elastic members with varying force characteristics. The elastic members are configured with different stiffness, pre-compression forces, or material properties to apply appropriate forces to different regions of the chip. This allows effective warpage correction through parameter optimization rather than increasing structural complexity.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method effectively reduces or prevents warpage of semiconductor chips during bonding, enhancing the reliability of electrical connections and preventing damage, thereby improving the stability and performance of semiconductor packages.

Implementation Method 1

a compressive member at least partially accommodated by the barrel and disposed between the barrel and the plunger

Methodology Applied
Scientific EffectElasticity: Elasticity

Implementation Method 2

a heat generator disposed on an upper surface of the housing and thermally connected to the plurality of elastic members

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS20240170448A1Semiconductor package manufacturing method and a bonding device for manufacturing a semiconductor package
Publication Date: 2024.05.23 SAMSUNG ELECTRONICS CO LTD
  • US20240170448A1 patent drawing
  • US20240170448A1 patent drawing
  • US20240170448A1 patent drawing

AI summary

A method of manufacturing a semiconductor package includes applying a plurality of forces to a plurality of points of a semiconductor chip through a plurality of elastic members, and bonding the semiconductor chip to an object while the plurality of forces are applied to the plurality of points of the semiconductor chip through the plurality of elastic members, wherein the plurality of elastic members are configured such that the plurality of forces are different from each other, and the plurality of forces flatten the semiconductor chip.