Elastic Wave Substrate Cavities for Lower Wiring Capacitance
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Solution Overview
Problem
Elastic wave devices often suffer from degraded characteristics due to parasitic capacitances between wiring lines, which affect their performance.
Innovation Solution
The design includes a support substrate with first and second hollow portions isolated by a partition wall, reducing parasitic capacitance by providing these hollows below wiring lines and an IDT electrode, and using an acoustic reflection film to enhance wave excitation without increasing manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wiring lines are provided on the piezoelectric substrate to connect to the IDT electrode, then electrical connectivity is achieved, but parasitic capacitance increases and device characteristics are degraded
Solution Approach 1:
The patent introduces hollow portions in the support substrate at positions corresponding to wiring lines and IDT electrodes, utilizing the vertical dimension (depth into the substrate) to reduce capacitance. By creating air-filled cavities below the conductive elements, the design adds a spatial dimension for capacitance reduction without affecting the planar wiring layout on the piezoelectric substrate surface.
Solution Approach 2:
The patent extracts the harmful capacitive coupling by removing material (creating hollow portions) from the support substrate beneath the wiring lines and IDT electrodes. This extraction of substrate material replaces the solid dielectric with air, thereby reducing the parasitic capacitance generated by the wiring structure.
2Reliability
If hollow portions are created in the support substrate to reduce parasitic capacitance, then device characteristics are improved, but mechanical strength may be compromised
Solution Approach 1:
The patent divides the support substrate into multiple regions by introducing partition walls that separate the hollow portions. This segmentation creates a structured framework within the substrate, where the partition walls act as mechanical reinforcements that maintain structural integrity while allowing the hollow portions to reduce parasitic capacitance in specific areas.
Solution Approach 2:
The patent applies hollow portions selectively at specific locations corresponding to wiring lines and IDT electrodes where parasitic capacitance is most problematic, rather than throughout the entire substrate. This localized approach reduces capacitance where needed while preserving the solid substrate structure in other areas to maintain mechanical strength.
3Object-generated harmful factors
If multiple hollow portions are provided for capacitance reduction, then parasitic capacitance is reduced, but device structure becomes more complex
Solution Approach 1:
The patent combines multiple hollow portions into a coordinated system where partition walls serve dual purposes: they structurally reinforce the substrate while simultaneously defining the boundaries of multiple hollow regions. This merging of structural and capacitive reduction functions into a single integrated design reduces overall complexity compared to implementing separate reinforcement structures and hollow portions independently.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces parasitic capacitance, improving the elastic wave device's characteristics and mechanical strength while maintaining efficient manufacturing processes.
Implementation Method 1
an acoustic reflection film that is stacked on a lower surface of the piezoelectric substrate below the IDT electrode. A plate wave may be excited by providing an acoustic reflection film below the IDT electrode in this manner.
Implementation Method 2
an IDT electrode that is provided on the piezoelectric substrate
Data Source
AI summary
In an elastic wave device, a piezoelectric substrate is stacked on a support substrate and an IDT electrode is provided on the piezoelectric substrate. Wiring line portions are provided on the piezoelectric substrate. A first hollow portion is provided in the support substrate at least below at least one of the wiring line portions and or below a region between the wiring line portions.