Electro-Optical Gate Layout for High-Speed Signal Writing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing electro-optical devices face challenges in high-speed driving due to performance differences between N-channel and P-channel transistors, primarily caused by equivalent capacitive couplings with light shielding films covering both transistors, leading to waveform rounding and insufficient signal writing.

Innovation Solution

The electro-optical device is designed with a light shielding film configuration where the film overlaps with one transistor but not the other, and employs a dual light shielding film system with varying light shielding properties to minimize capacitive coupling and performance differences, ensuring high-speed operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If the light shielding film covers the entire region of the transmission gate in plan view, then the light shielding effect is improved, but the capacitive coupling between the light shielding film and wiring lines becomes equivalent for both N-channel and P-channel transistors, preventing elimination of performance differences

Engineering Contradiction:
Improvelight shielding effectVSAvoidperformance difference elimination
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The light shielding film is designed with different coverage areas for N-channel and P-channel transistors. Specifically, the light shielding film covers the P-channel transistor but not the N-channel transistor, creating asymmetric light shielding that compensates for the inherent performance differences between the two transistor types. This local differentiation in light shielding coverage allows the weaker P-channel transistor to be protected from light interference while the N-channel transistor maintains its superior performance characteristics.

Inventive Principle:
Principle #3Local quality

2Object-affected harmful factors

If the light shielding film covers the entire region of the transmission gate, then light entering the transistor is blocked, but waveform rounding increases and signal writing becomes insufficient at high speeds

Engineering Contradiction:
Improvelight entering transistorVSAvoidsignal writing speed
Core Design Contradiction:
Object-affected harmful factorsVSSpeed

Solution Approach 1:

The light shielding film is strategically positioned to cover only the P-channel transistor region while leaving the N-channel transistor region uncovered. This asymmetric configuration reduces the overall capacitive coupling effect and minimizes waveform rounding, thereby improving signal writing speed while still providing necessary light shielding protection to the P-channel transistor.

Inventive Principle:
Principle #3Local quality

3Speed

If asymmetric light shielding film coverage is applied to compensate for transistor performance differences, then high-speed driving capability is improved, but the device complexity increases

Engineering Contradiction:
Improvedriving speedVSAvoidlight shielding film configuration
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The light shielding film is segmented into different coverage regions corresponding to different transistor types. Instead of a uniform coverage, the film is divided such that it covers the P-channel transistor but not the N-channel transistor. This segmentation approach, while increasing configuration complexity, enables optimized performance for each transistor type and achieves high-speed driving capability.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20260003236A1Electro-optical device and electronic apparatus
Publication Date: 2026.01.01 SEIKO EPSON CORP
  • US20260003236A1 patent drawing
  • US20260003236A1 patent drawing
  • US20260003236A1 patent drawing

AI summary

An electro-optical device includes: a first substrate; a second substrate; an electro-optical layer disposed between the first substrate and the second substrate; a display region including a plurality of pixels; and a peripheral area provided outside the display region, in which the first substrate includes: a transmission gate including an N-channel type transistor and a P-channel type transistor; an electrical conducting section closer to the electro-optical layer than the transmission gate; and a light shielding film closer to the electro-optical layer than the electrical conducting section, and the light shielding film overlaps with the electrical conducting section and one of the N-channel type transistor and the P-channel type transistor in plan view, and does not overlap with the other one of the N-channel type transistor and the P-channel type transistor in plan view.