Electro-optical Device Scanning Line Width Optimization
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Solution Overview
Problem
In electro-optical devices, the existing structure that overlaps the scanning line with the semiconductor layer to suppress light incidence results in a widened scanning line, leading to a reduction in pixel aperture ratio and inefficient light utilization due to the need for light shielding by the gate electrode inside openings in the semiconductor layer.
Innovation Solution
The electro-optical device incorporates a scanning line and a transistor with a semiconductor layer overlapping the scanning line, featuring interlayer insulating layers with first and second openings, where the gate electrode is positioned inside both openings, with the second opening not overlapping with the scanning line, allowing for efficient light shielding without widening the scanning line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the gate electrode is provided inside openings in the semiconductor layer to shield light, then light incidence on the LDD region is suppressed, but the scanning line width must be widened which reduces the pixel aperture ratio
Solution Approach 1:
The patent introduces a new spatial dimension by providing a second opening at a position not overlapping with the scanning line in plan view. This allows the gate electrode to be positioned in three-dimensional space to perform light shielding function without occupying additional width of the scanning line, thus resolving the contradiction between light shielding effectiveness and pixel aperture ratio maintenance
2Object-affected harmful factors
If the scanning line width is widened to accommodate the gate electrode for light shielding, then light shielding is achieved, but the pixel aperture ratio is reduced
Solution Approach 1:
The patent utilizes vertical stacking and offset positioning in the third dimension (depth/layer) and planar offset to achieve light shielding without increasing the scanning line width. The gate electrode is positioned in openings that are offset from the scanning line in plan view, allowing light shielding to occur in a different spatial location while maintaining the original scanning line dimensions and preserving pixel aperture ratio
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses light incidence on the semiconductor layer, reduces off-leak current, and maintains a high pixel aperture ratio by allowing a narrower scanning line, enhancing light utilization efficiency.
Implementation Method 1
a gate electrode having light shielding properties and disposed on a side, opposite from the scanning line, of the semiconductor layer
Data Source
AI summary
In an electro-optical device, in an interlayer insulating layer provided in a layer between a transistor and a scanning line, a first opening and a second opening are respectively provided on both sides of a semiconductor layer in plan view, and a portion of a gate electrode is provided inside each of the first opening and the second opening. Therefore, the gate electrode configures a light shielding wall inside each of the first opening and the second opening. Of the first opening and the second opening, the first opening is provided at a position overlapping with the scanning line in plan view, and the gate electrode is electrically connected to the scanning line via the first opening. The second opening is provided at a position that does not overlap with the scanning line in plan view. Thus, the width of the scanning line can be made narrower.