Electroluminescent Display Panel with Patterned Conductive Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional electroluminescent display panels face challenges with high parasitic capacitance, complex fabrication processes, and high manufacturing costs, as well as difficulties in precise alignment of oxide semiconductor layers during photolithography, which hinder their widespread adoption.
Innovation Solution
The proposed electroluminescent display panel structure includes a substrate with multiple-layered structural layers, passivation layers, and patterned conductive layers, where the oxide semiconductor layer is aligned precisely, and parasitic capacitance is reduced through specific patterning and conductivity-enhancing treatments, allowing for stable operation of switch and driving thin film transistor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If oxide semiconductor layers are used in conventional electroluminescent display panels, then transparency and self-luminous characteristics are achieved, but precise alignment in photolithography processes becomes difficult
Solution Approach 1:
The patent applies color changes by introducing a light-blocking layer with specific optical properties that contrasts with the transparent oxide semiconductor layer. This layer can be patterned to provide visual references during photolithography alignment, enabling precise positioning of subsequent layers while maintaining the transparency of the oxide semiconductor for self-luminous operation
Solution Approach 2:
The patent introduces an intermediary light-blocking layer between the substrate and the oxide semiconductor layer. This intermediary layer serves as an alignment reference during fabrication while not interfering with the electrical and optical functions of the oxide semiconductor, thus resolving the conflict between transparency and alignment precision
2Use of energy by moving object
If conventional electroluminescent display panel structures are used, then self-luminous characteristics are achieved, but parasitic capacitance between adjacent wires remains high
Solution Approach 1:
The patent applies segmentation by dividing the conductive layers into multiple separate patterned layers with insulation layers between them. This segmentation isolates adjacent wires electrically, reducing parasitic capacitance between them while maintaining the self-luminous characteristics of the electroluminescent display
Solution Approach 2:
The patent reduces parasitic capacitance by transitioning to a multi-layered vertical structure where conductive elements are separated in the vertical dimension through insulation layers. This dimensional separation effectively reduces the capacitive coupling between adjacent wires while preserving the horizontal connectivity needed for display operation
3Ease of manufacture
If conventional fabrication processes are used for electroluminescent display panels, then manufacturing is achieved, but the process complexity and cost are high
Solution Approach 1:
The patent merges multiple fabrication steps into integrated process sequences, combining the formation of conductive layers, insulation layers, and light-blocking layers into a unified multi-layered structure that can be manufactured using standard thin-film deposition and patterning techniques, thereby reducing overall process complexity
Solution Approach 2:
The patent employs universal materials and processes that can serve multiple functions: the light-blocking layer provides both optical contrast for alignment and electrical isolation, while the patterned conductive layers serve both as interconnects and as alignment references for subsequent fabrication steps, reducing the need for additional specialized process steps
Data Source
AI summary
An electroluminescent display panel and method of fabricating the same are provided. The electroluminescent display panel includes a first multiple-layered structural layer, a second multiple-layered structural layer, a passivation layer and a third patterned conductive layer. The first multiple-layered structural layer includes a first patterned conductive layer, a first patterned insulation layer and an oxide semiconductor layer, and the first patterned conductive layer, the first patterned insulation layer and the oxide semiconductor layer have substantially the same shape. The second multiple-layered structural layer includes a second patterned conductive layer. The passivation layer has a plurality of through holes. A portion of the through holes expose the top surface and the lateral surface of the oxide semiconductor layer and the lateral surface of the first patterned conductive layer. The third patterned conductive layer is in contact with the oxide semiconductor layer and the first patterned conductive layer via the through holes.


