Electromigration Susceptibility via Hydrostatic Stress Analysis
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Solution Overview
Problem
Conventional methods for detecting electromigration susceptibility in microcircuit interconnects are resource-intensive and impractical for full-chip analysis, failing to predict long-term degradation or failure rates due to electromigration.
Innovation Solution
The method involves analyzing circuit design layout data to determine voltages in an interconnect tree, computing current density and hydrostatic stress values, and comparing these against threshold values to assess electromigration susceptibility, using a matrix system based on parasitic resistance values and assuming steady-state conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional finite element analysis methods are used to detect electromigration susceptibility, then measurement precision is improved, but device complexity and computational resources required increase significantly making full-chip analysis impractical
Solution Approach 1:
The patent segments the interconnect structure into discrete segments between via holes, analyzing each segment independently using simplified equations rather than treating the entire structure as a continuous complex system. This segmentation allows full-chip analysis by breaking down the problem into manageable units that can be processed efficiently.
Solution Approach 2:
The patent extracts and focuses only on the critical parameters for electromigration analysis (current density, segment length, via hole positions) while eliminating unnecessary computational complexity of full finite element analysis. This extraction enables rapid assessment of electromigration risk without requiring exhaustive computational resources.
2Reliability
If conventional electromigration detection methods are used, then reliability assessment is improved for individual components, but productivity decreases due to inability to perform full-chip analysis
Solution Approach 1:
By segmenting the interconnect into discrete sections and applying simplified analysis equations to each segment, the method enables rapid evaluation across entire chips while maintaining reliability assessment accuracy for predicting electromigration failures.
Solution Approach 2:
The patent changes the analytical approach from continuous finite element parameters to discrete segment-based parameters (segment length L, current density J, via hole positions), enabling both reliable failure prediction and high productivity through efficient computation across full-chip designs.
3Measurement precision
If detailed finite element analysis is performed, then measurement precision for stress analysis is improved, but loss of time increases making long-term degradation prediction impractical
Solution Approach 1:
Segmentation of the interconnect structure enables rapid hydrostatic stress calculation by applying simplified equations to discrete segments rather than performing time-consuming continuous analysis, making long-term degradation prediction practical.
Solution Approach 2:
The method performs preliminary calculation of current density and hydrostatic stress using simplified segment-based equations before detailed reliability assessment, enabling rapid screening and reducing overall analysis time while maintaining prediction accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the identification of interconnects susceptible to electromigration, distinguishing between susceptible and immortal interconnects, thereby extending circuit lifetime by predicting and mitigating degradation.
Implementation Method 1
determining electromigration susceptibility of the interconnect tree based on the computed hydrostatic stress values
Implementation Method 2
computing, based on the current density values and the current directions, hydrostatic stress values for the nodes
Data Source
AI summary
Aspects of the invention relate to techniques for determining the electromigration features corresponding to layout design data. According to various examples of the invention, a circuit design is analyzed to determine voltages of nodes in an interconnect tree. From the voltages of the nodes, current density values and current directions for the segments of the interconnect tree are determined. Based on the current density values and the current directions, hydrostatic stress values for the nodes are computed under a steady-state condition and conservation of the conductive material within the interconnect tree. The electromigration susceptibility of the interconnect tree is then determined based on the computed hydrostatic stress values.


