Electronic Assembly Defect Detection Using Grid-Based Scratch Analysis
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Solution Overview
Problem
Current methods for detecting defects on electronic assemblies, such as scratches on semiconductor wafers, rely heavily on visual inspection and are inefficient, lacking accuracy and reliability, especially when dealing with complex patterns and multiple scratches.
Innovation Solution
A method and system that utilize a processing unit to create a grid of nodes representing electronic units on an assembly, determining straight and circular lines to identify failed units by matching specific criteria, thereby facilitating the detection of defects like scratches through computational analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If visual inspection by experienced experts is used to detect defects, then detection capability is maintained, but productivity is low and reliability is insufficient
Solution Approach 1:
The patent replaces manual visual inspection with an automated computational system that uses grid-based analysis and line-fitting algorithms to detect scratches and defects on semiconductor wafers. This substitution of mechanical/human inspection with computational methods simultaneously improves reliability through consistent algorithmic application and productivity through automated high-speed processing of wafer images.
2Productivity
If automated detection methods are implemented, then productivity increases, but measurement precision is insufficient for complex defect patterns
Solution Approach 1:
The patent divides the wafer surface into a grid of nodes, where each node represents a specific location. This segmentation allows the system to systematically analyze complex defect patterns by examining individual nodes and their relationships, thereby maintaining high measurement precision while enabling automated high-speed processing that improves productivity.
Solution Approach 2:
The patent transitions from analyzing raw pixel data to a grid-based representation where nodes are arranged in structured positions. This dimensional transformation enables the application of geometric algorithms (line fitting, angle calculation) that precisely characterize defect patterns while facilitating efficient computational processing.
3Speed
If simple detection criteria are used, then processing speed increases, but detection precision decreases for intersecting or close scratches
Solution Approach 1:
The patent performs preliminary actions by first identifying candidate lines through grid node analysis before applying more complex fitting algorithms. This staged approach allows the system to quickly filter obvious defects while applying more precise computational methods only where needed, maintaining high processing speed while ensuring accurate differentiation of complex scratch patterns.
4Reliability
If comprehensive analysis of all nodes is performed, then detection reliability improves, but loss of time increases
Solution Approach 1:
The patent applies partial analysis by focusing computational resources on nodes that form candidate defect patterns rather than uniformly processing all nodes. The line-fitting algorithm efficiently evaluates only relevant node combinations, achieving high detection reliability through targeted analysis while minimizing processing time by avoiding exhaustive examination of all possible node configurations.
Data Source
AI summary
A method of identifying defects in an electronic assembly, comprising, by a processing unit, obtaining a grid of nodes representative of a location of electronic units of an electronic assembly, wherein each node is neighboured by at most eight other nodes, wherein a first plurality of nodes represents failed electronic units according to at least one test criterion, and a second plurality of nodes represents passing electronic units according to the least one first test criterion, based on the grid, determining at least one first and second straight lines, and attempting to connect the first and second straight lines into a new line, wherein if at least one node from the new line belongs to the second plurality of nodes, concluding that an electronic unit represented by the node on the grid is a failed electronic unit, thereby facilitating identification of a failed electronic unit on the substrate.