Electronic Component Bump Design for Stress Relief
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Solution Overview
Problem
The reliability of bonding between a substrate and device chips is compromised due to stress caused by temperature loads, and existing solutions do not effectively manage this stress while minimizing the size of electronic components.
Innovation Solution
The electronic component design features device chips with larger bumps at corners facing each other, reducing stress on these bumps by increasing their diameter, and smaller bumps elsewhere to maintain component size and improve heat release performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bumps with larger diameter are used to reduce stress, then reliability of bonding is improved, but the size of the electronic component increases
Solution Approach 1:
The patent applies different bump diameters to different locations on the device chip. Specifically, bumps at corner pads have a first diameter while bumps at other pads have a second diameter. This local differentiation allows stress concentration management at critical corner locations without increasing the size of bumps across the entire component, thus improving bonding reliability at stress-prone areas while maintaining compact overall component size.
2Reliability
If larger bumps are used to reduce stress on bonding, then bonding reliability is improved, but heat release performance deteriorates
Solution Approach 1:
The patent implements local quality by using smaller diameter bumps at non-corner pads compared to corner pads. The corner bumps with larger diameter provide enhanced stress resistance at critical bonding locations, while the smaller bumps at other locations maintain better heat dissipation characteristics. This spatially differentiated bump design simultaneously addresses both bonding reliability and heat release performance by optimizing bump size according to local functional requirements.
Data Source
AI summary
An electronic component includes: four device chips having rectangular planar shapes and arranged on a substrate so that a corner of four corners constituting a rectangle of one device chip is adjacent to the corners of remaining three device chips; first pads located on surfaces of the four device chips and closest to the corner; one or more first bumps bonding the first pads to the substrate in the four device chips; second pads located on surfaces of the four device chips, the second pad being one of pads other than the first pad; and one or more second bumps bonding the second pads to the substrate in the four device chips, a sum of bonded areas between the one or more second bumps and the second pad being less than a sum of bonded areas between the first pad and the one or more first bumps.