Electronic Module With Stacked Wiring for Faster Signal Transmission
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The transmission properties of signal wirings in electronic modules are insufficient, limiting the ability to increase the transmission speed of signals, which in turn restricts the operating speed of semiconductor devices.
Innovation Solution
A three-dimensional mounting structure is employed, where two wiring boards are laminated with a wiring member connecting them, optimizing the placement of semiconductor devices and signal terminals to minimize signal wiring length and improve transmission properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the transmission property of signal wiring is insufficient, then the operating speed of semiconductor devices cannot be increased, but increasing the transmission speed requires improving the signal wiring properties which conflicts with conventional two-dimensional mounting limitations
Solution Approach 1:
The patent transitions from a conventional two-dimensional planar mounting structure to a three-dimensional stacked configuration where wiring boards are laminated in the vertical direction. This dimensional change allows signal terminals to be positioned closer together, significantly reducing signal wiring length and improving transmission properties without increasing the horizontal footprint of the device.
Solution Approach 2:
The patent implements a nested structure where multiple wiring boards are laminated one on top of another, with semiconductor devices mounted on different levels. The frame body is disposed between the wiring boards, creating a compact nested arrangement that reduces overall device size while maintaining efficient signal transmission paths.
2Area of stationary object
If two wiring boards are laminated to reduce mounting area, then the module size is reduced, but the signal wiring length increases which degrades transmission properties
Solution Approach 1:
By stacking wiring boards in the vertical dimension rather than expanding horizontally, the patent reduces the mounting area footprint while actually decreasing the signal wiring length. The vertical stacking allows for shorter horizontal wiring paths between adjacent components compared to conventional planar arrangements.
Solution Approach 2:
The frame body acts as an intermediary structure disposed between the laminated wiring boards, providing mechanical support and positioning that enables optimized signal wiring paths. This intermediary element facilitates the three-dimensional arrangement while maintaining signal integrity.
3Productivity
If semiconductor devices are positioned to maximize performance, then device operation efficiency is improved, but the signal wiring length increases which limits transmission speed
Solution Approach 1:
The patent positions semiconductor devices on different vertical levels of the laminated wiring boards, allowing high-performance device placement without excessive horizontal separation. This vertical distribution enables shorter signal wiring lengths while maintaining optimal device performance and connectivity.
Solution Approach 2:
The patent applies different mounting configurations to different regions of the wiring boards, with semiconductor devices strategically positioned on specific layers to optimize both performance and signal transmission. The frame body provides localized support structures that enable precise device positioning for optimal electrical connectivity.
Data Source
Figure 1
Figure 2
Figure 3A~3B
AI summary
An electronic module includes a first wiring board (11), a first semiconductor device (21), a second wiring board (12) configured to overlap with the first wiring board in a first direction (Z) orthogonal to a main surface (111) of the first wiring board, a second semiconductor device (22), and a wiring member (31). A first wiring terminal (3111) and a second wiring terminal (3112) of the wiring member are disposed between a first imaginary plane (V1) and a second imaginary plane (V2), the first imaginary plane being orthogonal to the main surface and configured to cross the first signal terminal, the second imaginary plane being parallel to the first imaginary plane and configured to cross the second signal terminal, and/or a first signal terminal (2111) and a second signal terminal (2112) of the first semiconductor device are configured not to overlap with the wiring member in the first direction.