Electronic Package Carrier Structure Design for Yield Improvement
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Solution Overview
Problem
Conventional semiconductor chip packaging techniques face challenges in yield reduction due to increased complexity and size requirements, particularly with the need for larger bonding areas and more conductive vias, which complicates manufacturing and hinders miniaturization efforts.
Innovation Solution
The use of a first electronic component as a carrier structure for passive components with fine lines and pitches, allowing for reduced size design and improved power supply stability, eliminating the need for a conventional package substrate and enabling miniaturized designs by stacking passive components and reducing the number of conductive vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a through silicon interposer with multiple TSVs is used to support more electronic components, then the electrical functionality is improved, but the manufacturing complexity and difficulty increase
Solution Approach 1:
The patent divides the through silicon interposer into multiple separate semiconductor chips, each containing a subset of the TSVs and circuit elements. This segmentation transforms a single complex manufacturing process into multiple simpler chip fabrication and assembly steps, reducing overall manufacturing complexity while maintaining the electrical functionality of having multiple TSVs and components.
2Adaptability or versatility
If a larger bonding area is provided to accommodate more electronic components, then the electrical functionality is improved, but the package substrate area increases
Solution Approach 1:
The patent transitions from a two-dimensional layout where all components are placed on a large substrate to a three-dimensional stacked configuration. Multiple semiconductor chips are vertically stacked and interconnected through conductive vias, enabling high electrical functionality within a compact footprint, thus reducing the required package substrate area.
3Adaptability or versatility
If more conductive vias are laid out to connect electronic components, then the electrical connectivity is improved, but the manufacturing yield decreases
Solution Approach 1:
The patent segments the conductive vias into different groups, with each semiconductor chip containing its own set of TSVs and conductive elements. This reduces the total number of vias that need to be aligned and connected in a single manufacturing process, thereby improving manufacturing yield while maintaining comprehensive electrical connectivity across all components.
4Adaptability or versatility
If a photomask with scale factor greater than 1 is used to manufacture large-sized SoC, then the compatibility with package substrate layout is improved, but the wafer yield decreases
Solution Approach 1:
Instead of scaling up the photomask to create large-sized SoCs that match the package substrate layout, the patent inverts the approach by using standard-sized chips with conventional photomask scales and achieving layout compatibility through vertical stacking and conductive via connections. This maintains high wafer yield while ensuring compatibility with the package substrate architecture.
Data Source
AI summary
An electronic package is provided, which is disposed with a second electronic component and a third electronic component on a first electronic component as a carrier structure, such that there is no need to match a layout size of the conventional package substrate. Therefore, the first electronic component can be designed as a System on a Chip (SoC) with a smaller size to improve the process yield.