Electronic Paper Active Substrate Storage Capacitance
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Solution Overview
Problem
Current electronic paper display panels face challenges in increasing storage capacitance without compromising the properties of Thin Film Transistor (TFT) devices, as existing methods either occupy significant pixel area or risk breakdown with thin gate insulating layers.
Innovation Solution
A method involving the formation of a second common electrode between the passivation and resin passivation layers, connected through a via hole, which increases the area of the capacitor plates, effectively doubling the storage capacitance without negatively impacting TFT properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the source-drain electrode is spread in a large area to increase storage capacitance, then the capacitance increases, but the pixel area is limited and this measure has less effect
Solution Approach 1:
The patent extends the capacitor structure into the vertical dimension by forming a protrusion on the common electrode that rises through the gate insulating layer. This three-dimensional configuration increases the effective plate area without consuming additional horizontal pixel area, thereby resolving the contradiction between increasing capacitance and maintaining limited pixel footprint.
Solution Approach 2:
The protrusion structure is nested within the existing pixel structure, with the common electrode protrusion embedded in the gate insulating layer and the pixel electrode formed around it. This nested configuration allows the capacitor to be integrated within the pixel without requiring separate dedicated capacitor area, effectively increasing capacitance within the constrained pixel area.
2Quantity of substance
If the gate insulating layer is made thinner to increase capacitance, then the capacitance increases, but short or breakdown between gate electrode and source-drain electrodes may occur
Solution Approach 1:
Instead of reducing gate insulating layer thickness, the patent creates vertical protrusions that extend through the existing thickness of the gate insulating layer. This approach increases capacitance by adding plate area in the vertical dimension while preserving the original gate insulating layer thickness, thereby maintaining TFT reliability and preventing short circuits.
3Quantity of substance
If a resin passivation layer is added to reduce parasitic capacitance and spread the pixel electrode layer, then the pixel electrode area increases, but the manufacturing process becomes more complex
Solution Approach 1:
The protrusion structure is formed on the common electrode before depositing the gate insulating layer and subsequent layers. This preliminary formation of the three-dimensional structure allows subsequent layers to be deposited conformally, naturally following the protrusion contours and creating the necessary via holes and electrode connections without requiring additional complex manufacturing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases storage capacitance, nearly doubling it, while maintaining the integrity and performance of TFT devices, thus enhancing the electronic paper display panel's ability to handle high voltages and reduce leakage current.
Implementation Method 1
a second via hole forming step for forming a second via hole which passes through the passivation layer and the gate insulating layer, so that a portion of the first common electrode is exposed through the second via hole
Data Source
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AI summary
Embodiments of the invention disclose an electronic paper active substrate and a method of forming the same and an electronic paper display panel. The electronic paper active substrate comprises: a base substrate, a gate electrode, a first common electrode, a second common electrode, a gate insulating layer, an active layer, source-drain electrodes, a passivation layer, a resin passivation layer, and a pixel electrode layer. The gate electrode and the first common electrode are arranged on the base substrate, and the gate is provided with the gate insulating layer, the active layer, the source-drain electrodes, the passivation layer, the resin passivation layer, and the pixel electrode layer sequentially arranged thereon; the first common electrode is provided with the gate insulating layer, the source-drain electrodes, the passivation layer, the second common electrode, the resin passivation layer, and the pixel electrode layer sequentially arranged thereon; and the first and second common electrodes are electrically connected to each other.