Elevationally-Extending Transistor Memory Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory cell technologies face challenges in forming arrays of memory cells with capacitors and elevationally-extending transistors, particularly in efficiently patterning and integrating these components within the array structure without sacrificing performance or reliability.
Innovation Solution
The method involves using two sacrificial masking steps to pattern digit lines and channel-comprising materials, forming elevationally-extending pillars for transistors, and integrating capacitors with specific electrode configurations to ensure accurate and reliable memory cell formation, utilizing techniques like anisotropic etching and dielectric materials to achieve precise alignment and functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional memory cell formation methods are used, then manufacturing process is simpler, but manufacturing precision and alignment accuracy deteriorate
Solution Approach 1:
The patent applies preliminary action by forming sacrificial masks and placeholder structures before final patterning. The method uses preliminary deposition of dielectric materials and conductive layers that are later selectively removed or transformed, enabling precise alignment of capacitors with transistor channels without requiring complex real-time alignment procedures.
Solution Approach 2:
The patent uses sacrificial masks and placeholder structures as intermediary elements. These temporary structures serve as mediators to define precise locations for capacitor formation and ensure accurate alignment with transistor channels. The sacrificial materials are later removed or transformed, leaving the precisely aligned final structure without requiring direct complex patterning.
2Quantity of substance
If component density is increased, then storage capacity improves, but integration difficulty increases
Solution Approach 1:
The patent transitions from two-dimensional planar patterning to three-dimensional vertical structures. By forming elevationally-extending transistor channels and positioning capacitors in vertical alignment, the method achieves higher component density without proportionally increasing lateral integration complexity. The vertical dimension provides additional space for capacitor placement while maintaining manageable lateral patterning.
Solution Approach 2:
The patent segments the memory cell structure into distinct functional regions: elevationally-extending transistor channels, separately-formed capacitors with precise alignment, and interconnecting conductive layers. This segmentation allows each component to be optimized and formed independently using standardized processes, reducing overall integration difficulty while increasing density.
3Reliability
If capacitor alignment with transistor channels is made more precise, then device reliability improves, but process complexity increases
Solution Approach 1:
The patent implements self-service alignment where the sacrificial masks and placeholder structures automatically define the precise locations for capacitor formation. The alignment is achieved through self-aligned processes where subsequent layers are deposited or etched relative to previously formed structures, eliminating the need for separate complex alignment procedures and ensuring high precision automatically.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of robust and efficient arrays of memory cells with capacitors and elevationally-extending transistors, enhancing storage capabilities and operational reliability by ensuring precise patterning and integration of components within the array structure.
Implementation Method 1
utilizing techniques like anisotropic etching and dielectric materials to achieve precise alignment and functionality
Implementation Method 2
A capacitor has two electrical conductors separated by electrically insulating material. Energy as an electric field may be electrostatically stored within such material.
Data Source
AI summary
A method of forming a tier of an array of memory cells within an array area, the memory cells individually comprising a capacitor and an elevationally-extending transistor, the method comprising using two, and only two, sacrificial masking steps within the array area of the tier in forming the memory cells. Other methods are disclosed, as are structures independent of method of fabrication.