Non-cylindrical Elongated Vias for High Current Density in Substrate Cores
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Solution Overview
Problem
Conductive vias in semiconductor packages face limitations in transferring high current density due to their cylindrical shape, which restricts power delivery and signal transmission, especially as semiconductor dies become smaller and require more power, leading to increased resistance and area requirements.
Innovation Solution
The implementation of non-cylindrical, copper-filled elongated vias in multilayer cores, created through laser drilling and milling, which reduces lateral resistance and allows for more efficient power delivery by increasing the number of layers available for routing, using techniques like electro-less copper plating and deburring to ensure uniform filling and connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If cylindrical through holes are used for power and signal transmission, then the structure is simple and easy to manufacture, but the current carrying capacity is limited and resistance is high
Solution Approach 1:
The patent transitions from symmetric cylindrical vias to asymmetric elongated vias with rectangular or oval cross-sections. This asymmetric shape increases the cross-sectional area available for current flow while maintaining manufacturability through laser drilling and electroplating processes, thereby improving current carrying capacity without sacrificing ease of manufacture
Solution Approach 2:
The patent extends the via structure from a two-dimensional circular cross-section into the third dimension by creating elongated shapes that traverse multiple layers. This dimensional extension increases the effective conductive path area and reduces resistance, enabling higher current density while maintaining structural integrity across multiple substrate layers
2Productivity
If more power is delivered through smaller semiconductor dies, then device integration increases, but resistance in through holes increases and power delivery becomes less efficient
Solution Approach 1:
The patent changes the geometric parameters of the via structure by increasing the cross-sectional area and elongating the shape. This parameter change reduces electrical resistance according to the resistance formula R=ρL/A, where increased area A directly reduces resistance, enabling efficient power delivery to highly integrated smaller dies
Solution Approach 2:
The patent uses composite construction by combining multiple materials: copper or other conductive materials are electroplated or filled into the elongated via structures. This composite approach creates low-resistance pathways that efficiently conduct power to high-density die arrangements, reducing energy loss while supporting increased device integration
3Object-affected harmful factors
If Faraday Cage-like structures are constructed with spaced apart PTHs, then electromagnetic shielding is provided, but the area required on the core increases significantly
Solution Approach 1:
The patent merges the via structure with the Faraday Cage shielding function by making the elongated via walls themselves conductive and continuous. This integration eliminates the need for separate spaced PTHs to create shielding, as the elongated via structure provides both electrical connection and electromagnetic shielding in a single compact element, reducing the area required on the core
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces resistance by 30-50% in through-silicon vias, enabling higher current density and more effective power transfer within the package substrate, while also allowing for more efficient signal transmission and reduced noise interference.
Implementation Method 1
Laser drilling and milling may be used to create a copper filled via or a copper filled non-cylindrical shape in an SVLC (Stacked Via Laminate Core) type core
Implementation Method 2
using techniques like electro-less copper plating and deburring to ensure uniform filling and connectivity
Data Source
AI summary
Non-cylindrical conducting shapes are described in the context of multilayer laminated substrate cores. In one example a package substrate core includes a plurality of dielectric layers pressed together to form a multilayer core, a conductive bottom pattern on a bottom surface of the multilayer core, and a conductive top pattern on a top surface of the multilayer core. At least one elongated via extends through each layer of the multilayer core, each elongated via containing a conductor and each connected to a conductor of a via in an adjacent layer to electrically connect the top pattern and the bottom pattern through the conductors of the elongated vias.