Embedded Anti-Fuse Liner Layout for Narrow-Pitch Interconnects
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Solution Overview
Problem
As interconnect dimensions scale down in integrated circuits, it becomes challenging to fabricate anti-fuses due to their bulkiness, which occupies considerable space, making it difficult to pack interconnect metal wires and other components efficiently.
Innovation Solution
The development of an anti-fuse with laterally extended metallic liners, where the metal tips of the barrier layers act as the weak point, allowing for an embedded anti-fuse that can be integrated into interconnects with sub-15 nm spacing and precise control over the spacing between metal tips, enabling integration into narrow-pitch interconnects without significant space consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional anti-fuse structures are used, then the anti-fuse can perform its breaking function, but it occupies considerable space making it difficult to pack interconnect metal wires efficiently
Solution Approach 1:
The anti-fuse structure transitions from a vertical configuration to a lateral configuration. The metallic liner extends laterally beneath the second low-k dielectric layer, with metal tips forming in opposite directions. This lateral extension allows the anti-fuse to occupy minimal vertical space while maintaining functionality, enabling efficient packing of interconnect metal wires in the available area.
Solution Approach 2:
The anti-fuse structure is nested within the interconnect layers. The metallic liner is embedded beneath the second low-k dielectric layer, and the structure integrates with existing interconnect components such as vias and trenches. This nesting allows the anti-fuse to share space with other interconnect elements, reducing overall space consumption.
2Productivity
If interconnect dimensions are scaled down, then integration density increases, but fabrication of anti-fuses becomes challenging due to their bulkiness
Solution Approach 1:
The anti-fuse structure is segmented into distinct functional components: a metallic liner layer, second low-k dielectric layer with trenches, and metal tips forming in opposite directions. This segmentation allows each component to be fabricated using standard semiconductor processes, making the overall structure easier to manufacture at scaled dimensions while maintaining integration density.
Solution Approach 2:
The structure uses different materials and properties in different locations: low-k dielectric material in specific regions for electrical isolation, metallic liner for conductivity, and selective trench formation. This local differentiation of material properties enables precise control over the anti-fuse behavior at scaled dimensions while facilitating easier fabrication through targeted process application.
3Manufacturing precision
If conventional anti-fuse structures are used, then the anti-fuse can be formed, but precise control over spacing between metal tips cannot be achieved
Solution Approach 1:
The metallic liner is deposited and configured before the second low-k dielectric layer is fully formed. Trenches are then etched through the dielectric layer to expose specific portions of the underlying metallic liner. This preliminary configuration of the metallic liner structure enables precise control over where metal tips will form, allowing accurate spacing control while managing device complexity through sequential processing.
Solution Approach 2:
The second low-k dielectric layer acts as an intermediary that controls the formation and spacing of metal tips. By etching trenches through this dielectric layer, the exposed portions of the metallic liner are precisely defined, thereby controlling the spacing between metal tips. This intermediary layer simplifies the overall structure while achieving the desired precision.
Data Source
AI summary
A capping layer is on top of a substrate. A first low-k dielectric layer is on top of the capping layer. One or more trenches are within the first low-k dielectric layer. Each of the one or more trenches have a same depth. Each trench of the one or more trenches include a barrier layer on top of the first low-k dielectric layer, a liner layer and a metal layer on top of the liner layer.