Embedded Bridge Interconnect for High-Density Die Routing
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Solution Overview
Problem
Current technologies face challenges in achieving high-density die-to-die connections in CPU packages due to bandwidth limitations and the difficulty in scaling via pitch in organic package substrates, which hinders the miniaturization trend and overall CPU performance.
Innovation Solution
The implementation of an embedded bridge interconnect assembly using a bridge substrate composed of glass or semiconductor material with high resistivity, featuring interconnect structures and conductive lines to route electrical signals between dies, and the use of vias filled with conductive material to enhance connectivity and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If ultra-small interconnection paths (via) with smallest possible interconnection pitches are used to connect through the package to the embedded bridge die, then high density die-to-die interconnection is achieved, but it becomes extremely difficult to scale via pitch in organic package substrate to desired size with current technology
Solution Approach 1:
The patent transitions from planar 2D organic substrate routing to 3D vertical interconnection through the embedded silicon bridge die. By stacking dies vertically and using through-silicon vias (TSVs) in the bridge die, the design achieves high-density interconnection in the vertical dimension rather than continuing to compress horizontal via pitch in organic substrates, thereby avoiding the manufacturing scaling limitations of current organic substrate technology
Solution Approach 2:
The patent changes the substrate material parameter from organic substrate to silicon bridge die with different via scaling characteristics. Silicon technology enables smaller via pitches through established TSV fabrication processes, allowing the interconnection pitch parameter to be reduced to desired sizes that are difficult to achieve in organic substrates
2Productivity
If multiple die are integrated within the CPU package in side-by-side or multi-chip-package format to enhance performance, then CPU performance improvement is achieved, but bandwidth limitations between logic-logic and/or logic-memory communications occur
Solution Approach 1:
The patent moves from 2D side-by-side die arrangement to 3D vertical stacking configuration. Multiple dies are stacked vertically with the silicon bridge die positioned between them, enabling three-dimensional integration. This vertical arrangement increases interconnection density and bandwidth capability by providing multiple interconnection layers and paths in the vertical dimension, overcoming the bandwidth limitations of planar MCP configurations
Solution Approach 2:
The embedded silicon bridge die acts as an intermediary component between the logic die and memory die. It provides high-density interconnection pathways that mediate the communication between these dies, enabling enhanced bandwidth for logic-logic and logic-memory communications without requiring direct high-bandwidth interfaces between all die pairs
Data Source
AI summary
Embodiments of the present disclosure are directed towards techniques and configurations for interconnect structures embedded in a package assembly including a bridge. In one embodiment, a package assembly may include a package substrate, a bridge embedded in the package substrate and including a bridge substrate, and an interconnect structure including a via extending through the package substrate into a surface of the bridge substrate and configured to interface with a conductive feature disposed on or beneath the surface of the bridge substrate. The interconnect structure may be configured to route electrical signals between the conductive feature and a die mounted on the package substrate. Other embodiments may be described and/or claimed.