Embedded Capacitor Connection Structure in Semiconductor Packages
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Solution Overview
Problem
There is a need to improve the connection structure between a capacitor embedded in a semiconductor package substrate and the connection patterns to ensure efficient and precise electrical connection, as existing methods do not effectively manage the application of ground and power supply voltages to the capacitor electrodes.
Innovation Solution
The semiconductor package includes a package substrate with embedded first and second wirings, where the capacitor has electrodes connected to these wirings, and a group of connection terminals that are physically separated but electrically connected through via contacts, allowing for efficient voltage application and stable electrical pathways.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If connection terminals are directly connected to capacitor electrodes through embedding, then manufacturing complexity is reduced, but electrical connection precision and stability deteriorate
Solution Approach 1:
The patent introduces connection patterns as intermediary elements between the capacitor electrodes and connection terminals. These connection patterns are formed on the package substrate surface and provide a controlled, precise interface that ensures accurate electrical connection while maintaining manufacturing feasibility. The connection patterns act as a mediator that bridges the gap between the embedded capacitor and the external connection terminals.
Solution Approach 2:
The patent transitions from direct vertical embedding connection to a multi-dimensional connection structure. Connection patterns are formed on the surface plane of the package substrate, extending the connection path from a single-point vertical connection to a distributed planar pattern. This dimensional change allows for improved connection precision through pattern design while maintaining the embedded capacitor structure.
2Reliability
If connection terminals are grouped continuously adjacent to each other, then electrical connection stability is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple connection terminals into continuous adjacent groups, forming integrated connection regions. These grouped terminals are connected through the connection patterns on the package substrate, creating unified electrical connection zones that enhance stability. The merging of terminals into continuous groups reduces the number of discrete connection points while improving overall connection reliability.
Solution Approach 2:
The connection patterns serve multiple functions: they provide electrical connection pathways, define terminal grouping regions, and establish stable electrical interfaces. This multi-functionality allows the same structural elements to achieve both connection stability and simplified overall design, counteracting the apparent increase in complexity.
3Volume of stationary object
If capacitor is embedded in package substrate, then package size is reduced, but electrical connection reliability deteriorates
Solution Approach 1:
The connection patterns on the package substrate surface act as intermediary elements that ensure reliable electrical connection between the embedded capacitor and external terminals. This mediator structure compensates for the potential reliability issues introduced by embedding, maintaining connection reliability while achieving compact packaging.
Solution Approach 2:
The patent segments the electrical connection path into distinct functional zones: the embedded capacitor region within the substrate, the connection patterns on the substrate surface, and the external connection terminals. This segmentation allows each component to be optimized for its specific function, ensuring that the embedded capacitor maintains reliable electrical connection despite the compact integrated structure.
Data Source
AI summary
A semiconductor package includes a package substrate including a first wiring embedded in the package substrate, a second wiring embedded in the package substrate, the second wiring electrically insulated from the first wiring, and a capacitor embedded in the package substrate, the capacitor including a first electrode electrically connected to the first wiring and a second electrode electrically connected to the second wiring. At least a first semiconductor chip is disposed on the package substrate. A plurality of connection terminals are disposed between the package substrate and the first semiconductor chip and contact the package substrate, and form at least a first group of at least two connection terminals formed continuously adjacent to each other and electrically connected to the first wiring, and at least a second group of at least two connection terminals formed continuously adjacent to each other and electrically connected to the second wiring.