Embedded Capacitor Core Multiple-Layer PCB Structure

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Solution Overview

Problem

Conventional surface mount capacitors on printed circuit boards (PCBs) face challenges due to their limited capacitance range, signal frequency handling, and spatial constraints, leading to undesirable inductance effects and noise interference, especially as electronic circuits become faster and devices shrink.

Innovation Solution

An embedded capacitor core with a multiple-layer structure is integrated into the PCB, comprising conductive patterns and dielectric layers, allowing for a high-dielectric-constant capacitor device with conductors buried on both sides of the dielectric layer, reducing wiring paths and providing a wide frequency bandwidth for noise suppression.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If surface mount capacitors are used on PCB, then capacitance storage function is provided, but wiring path length increases causing inductance effects

Engineering Contradiction:
Improvesignal integrityVSAvoidwiring path length
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The capacitor is merged with the PCB structure by embedding it within the board layers. The conductive patterns are formed directly on PCB substrates, and the capacitor is integrated into the multilayer structure, eliminating the need for separate surface mount components and long wiring paths.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The capacitor is nested within the PCB's multilayer structure. Conductive patterns are embedded between dielectric layers, with the capacitor physically contained within the board's internal layers, similar to a nested doll structure where one component is placed inside another.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If surface mount capacitors are used on PCB, then capacitance storage function is provided, but board space is consumed

Engineering Contradiction:
Improvecapacitance functionVSAvoidboard space
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The capacitor is moved from a two-dimensional surface mount configuration to a three-dimensional embedded structure within the PCB layers. This vertical integration utilizes the z-dimension of the multilayer board, freeing up surface area while maintaining capacitance functionality.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If conventional capacitor structures are used, then manufacturing simplicity is maintained, but frequency bandwidth is limited

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidfrequency bandwidth
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The capacitor utilizes a composite structure combining dielectric materials with high dielectric constants and conductive patterns. This composite approach enables the capacitor to handle wider frequency ranges while being manufactured using standard PCB fabrication processes.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution reduces power/ground bounce and signal noise, minimizes electromagnetic interference, and optimizes PCB space usage by embedding capacitors within the board, enhancing signal integrity and reducing inductance effects.

Implementation Method 1

a first dielectric layer between the first and second conductive films

Methodology Applied
Scientific EffectDielectric: Dielectric

Data Source

PatentUS7893359B2Embedded capacitor core having a multiple-layer structure
Publication Date: 2011.02.22 IND TECH RES INST
  • US7893359B2 patent drawing
  • US7893359B2 patent drawing
  • US7893359B2 patent drawing

AI summary

An embedded capacitor core including a first set of capacitors, a second set of capacitors, and an inter-layer dielectric film between the first set of capacitors and the second set of capacitors. The first set of capacitors includes: a first conductive pattern comprising at least two conductive electrodes; a second conductive pattern comprising at least two conductive electrodes corresponding to the two conductive electrodes of the first conductive pattern; and a first dielectric film between the first conductive pattern and the second conductive pattern. The second set of capacitors includes: a third conductive pattern comprising at least two conductive electrodes; a fourth conductive pattern comprising at least two conductive electrodes corresponding to the two conductive electrodes of the third conductive pattern; and a second dielectric film between the third conductive pattern and the fourth conductive pattern.