Embedded Capacitor Redistribution Layer for Smaller Semiconductor Packages
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Solution Overview
Problem
Semiconductor packages with embedded capacitors face challenges in achieving high device density and performance due to increased size and size, particularly when including passive devices such as capacitors and resistors, which can increase the semiconductor device size and hinder performance.
Innovation Solution
The semiconductor device incorporates a redistribution layer with at least one insulation layer in which a plurality of wiring patterns are formed; at least one semiconductor chip is disposed above or below the redistribution layer, and at least one capacitor is disposed in the redistribution layer, closer to the top surface facing the semiconductor chip than the bottom surface, and the capacitor can be disposed in the redistribution layer to be closer to the semiconductor chip than the bottom surface of the redistribution layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If passive devices such as capacitors and resistors are included in the semiconductor package, then the device functionality is improved, but the package size increases
Solution Approach 1:
The capacitor is embedded within the redistribution layer structure, with capacitor electrodes integrated into the wiring patterns and capacitor dielectric material positioned between adjacent wiring patterns within the same dielectric layer. This nesting approach allows the capacitor to occupy space that would otherwise be unused, eliminating the need for separate dedicated capacitor areas and reducing overall package size while maintaining full functionality.
Solution Approach 2:
The capacitor structure is merged with the redistribution layer wiring structure, where capacitor electrodes share the same conductive material and formation process as the wiring patterns, and the capacitor dielectric material is integrated into the dielectric layers already present in the redistribution structure. This merging eliminates redundant structures and reduces the total package footprint.
2Reliability
If the capacitor is disposed closer to the semiconductor chip, then the power delivery performance is improved by reducing noise and impedance, but the manufacturing complexity increases
Solution Approach 1:
The capacitor electrodes are formed simultaneously with the wiring patterns during the same photolithography and deposition processes, and the capacitor dielectric material is deposited along with the other dielectric layers before final planarization. This preliminary formation of capacitor structures during standard manufacturing steps eliminates the need for additional processing steps and reduces manufacturing complexity while achieving the desired close proximity to the semiconductor chip for optimal power delivery performance.
Data Source
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AI summary
Provided is a semiconductor device comprising a redistribution layer comprising: an insulation layer in which a first wiring pattern is formed; a first semiconductor chip, on the redistribution layer in a first direction, connected to the first wiring pattern; and a first capacitor disposed in the redistribution layer.