Embedded Capacitor Module Using Solid Electrolyte for High-Capacitance Decoupling
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Solution Overview
Problem
Current technologies for embedding capacitors in substrates face limitations in increasing capacitance beyond 0.1 uF due to the dielectric constant of organic insulating materials and the resulting equivalent series inductance, which cannot meet the demands of high-frequency signal transmission in portable electronic devices.
Innovation Solution
An embedded capacitor module using a solid electrolytic capacitor structure with a large-area metal substrate and conductive polymer layers, where the capacitor is embedded closer to the IC device, allowing for a greater surface area and enhanced capacitance without disrupting the existing circuitry, enabling capacitance values from several nF to hundreds of uF.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the dielectric constant of organic insulating material is increased to increase capacitance, then the capacitance can be increased, but the process yield decreases and fabrication cost increases
Solution Approach 1:
The patent changes the fundamental parameter of the dielectric material from organic insulating material to solid electrolytic material. This parameter change enables achieving high capacitance (hundreds of uF) without the drawbacks of increasing organic material dielectric constant, thereby maintaining process yield while significantly increasing capacitance.
Solution Approach 2:
The patent employs a composite structure consisting of multiple layers: anode layer, solid electrolyte layer, cathode layer, and current collector layers. This composite material approach enables the capacitor to achieve high capacitance through the synergistic effect of different materials, avoiding the need to increase dielectric constant of a single organic material.
2Quantity of substance
If more layers of embedded planar capacitor are added to increase capacitance, then the capacitance can be increased, but the substrate thickness and area requirements increase
Solution Approach 1:
The patent changes the capacitor structure from a planar multi-layer configuration to a solid electrolytic capacitor configuration. This parameter change allows achieving high capacitance (hundreds of uF) in a single compact unit without requiring multiple layers or increased substrate thickness.
3Object-affected harmful factors
If SMD capacitors are placed on the surface of IC carrier board to reduce impedance, then the impedance can be reduced, but the equivalent series inductance cannot be sufficiently suppressed due to limited area
Solution Approach 1:
The patent embeds the solid electrolytic capacitor directly within the substrate structure, nesting the capacitor inside the IC carrier board rather than placing it on the surface. This nesting approach minimizes the equivalent series inductance by reducing the area of the power delivery path, achieving low impedance without requiring additional surface area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a high-capacitance, low-impedance decoupling capacitor with a wide frequency band, effectively reducing noise interference and stabilizing power delivery in IC carrier boards, while allowing for integration into printed circuit boards without compromising the existing circuit structure.
Implementation Method 1
The solid electrolytic capacitor portion comprises a porous layer, an oxide layer, a conductive polymer layer, a carbon layer, and a conductive adhesive layer
Implementation Method 2
The embedded capacitor module uses a solid electrolytic capacitor structure to increase the capacitance
Data Source
AI summary
An embedded capacitor module includes an electrode lead-out portion and at least one solid electrolytic capacitor portion adjacently disposed with the electrode lead-out portion. The electrode lead-out portion comprises a first substrate, a second substrate, a first insulating material disposed between the first substrate and the second substrate, a first porous layer formed on at least one surface of the first substrate, and a first oxide layer disposed on the first porous layer. The solid electrolytic capacitor portion comprises the first substrate, the second substrate, the first porous layer, the first oxide layer, all of which are extended from the electrode lead-out portion, a first conductive polymer layer disposed on the first oxide layer, a first carbon layer disposed on the first conductive polymer layer, and a first conductive adhesive layer disposed on the first carbon layer.