Embedded Capacitor Substrate With Copper Pillar Via
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Solution Overview
Problem
Current methods for integrating passive elements like capacitors and inductors into circuit designs are complex, costly, and time-consuming, leading to increased resistance and power consumption due to long circuit lengths and high manufacturing costs.
Innovation Solution
A substrate structure is created with a copper pillar and capacitive element using a method involving multiple build-up circuit structures and dielectric layers, where the copper pillar penetrates the dielectric layer to connect the structures, simplifying the process and reducing costs while increasing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If discrete capacitors are soldered directly on substrate or embedded in dielectric material layer, then capacitance is achieved, but circuit length increases causing increased resistance and power consumption
Solution Approach 1:
The capacitive element is embedded within the substrate structure itself, nested between dielectric layers and integrated with circuit traces. This nesting approach places the capacitor in close proximity to the circuit nodes it serves, minimizing connection length while maintaining capacitance function.
Solution Approach 2:
The invention transitions from planar capacitor placement to three-dimensional integration within the substrate. By utilizing vertical stacking of dielectric layers and embedding capacitive elements between layers, the design achieves short circuit paths in the vertical dimension while maintaining compact horizontal footprint.
2Reliability
If miniaturized capacitive elements are produced via wafer process, then thinner capacitor with greater capacitance is obtained, but manufacturing complexity increases and quality control becomes difficult
Solution Approach 1:
The manufacturing process is segmented into standard semiconductor fabrication steps (forming conductive layers, dielectric layers, and patterned structures) that can be performed using existing CMOS-compatible processes. This segmentation allows each layer to be formed independently with controlled parameters, simplifying quality control while achieving miniaturized capacitive elements.
Solution Approach 2:
The invention achieves miniaturization by changing geometric parameters of the capacitive element structure, such as reducing layer thickness, optimizing electrode area, and adjusting dielectric constant through material selection. These parameter changes enable high capacitance density using standard fabrication processes without requiring complex wafer-level processing.
3Reliability
If inductor is formed by through-glass via (TGV), then inductance is achieved, but manufacturing cost increases and production time lengthens reducing yield
Solution Approach 1:
The invention extracts the inductive function from the substrate structure itself rather than forming it through complex TGV processes. By utilizing planar spiral or meander traces formed in standard conductive layers, the inductance is achieved without requiring through-glass via fabrication, thereby reducing manufacturing cost and improving yield.
Solution Approach 2:
The invention employs simple, inexpensive conductive trace patterns that can be formed using standard photolithography and metal deposition processes. These planar inductor structures replace expensive TGV-based inductors, achieving acceptable inductance values with much lower manufacturing cost and higher production yield.
Data Source
AI summary
A manufacturing method of a substrate structure includes the following steps. A first build-up circuit structure is formed. At least one copper pillar is formed on the first build-up circuit structure. A dielectric layer is formed on the first build-up circuit structure, and the dielectric layer wraps the copper pillar. A second build-up circuit structure and a capacitive element are formed on the dielectric layer. In particular, the second build-up circuit structure and the first build-up circuit structure are respectively located at two opposite sides of the dielectric layer. The capacitive element is disposed in a capacitive element setting region within the second build-up circuit structure. The copper pillar penetrates the dielectric layer and is electrically connected to the second build-up circuit structure and the first build-up circuit structure. A substrate structure obtained by the manufacturing method of the substrate structure is provided.