Embedded Charge Storage Transistor for Non-Volatile Memory
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Solution Overview
Problem
Non-volatile memory structures with high-k metal gate transistors face reduced charge storage capacity due to charge trapping by high-k material layers.
Innovation Solution
The implementation of an embedded-type charge storage transistor with a charge trapping layer, such as silicon nitride or nano-dots, and a selection transistor with a metal gate structure, which avoids the high-k/metal gate configuration, allowing for improved charge storage and reduced charge trapping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high-k material layer is integrated in the charge storage transistor, then gate leakage is reduced and processing speed is improved, but charge storage capacity is reduced due to charge trapping
Solution Approach 1:
The invention divides the memory structure into two separate transistors: a selection transistor with high-k metal gate for controlling gate leakage and processing speed, and a charge storage transistor without high-k material for maintaining charge storage capacity. This segmentation allows each transistor to be optimized for its specific function without the conflicting requirements that would arise from using high-k material in both structures.
Solution Approach 2:
The invention applies different material qualities to different locations in the memory structure. The selection transistor uses high-k metal gate materials (such as HfO2, ZrO2) to achieve low gate leakage and fast processing, while the charge storage transistor uses conventional gate materials that do not trap charges, ensuring high charge storage capacity. This local differentiation of material properties resolves the contradiction between gate performance and charge storage.
2Speed
If high-k metal gate transistor structure is used, then processing speed is improved, but charge trapping occurs reducing storage capability
Solution Approach 1:
The memory device is segmented into two functional units: a selection transistor with high-k metal gate for fast processing speed, and a charge storage transistor without high-k material for charge storage capability. This functional segmentation allows speed optimization in one component without compromising storage capability in the other.
Solution Approach 2:
Instead of using high-k metal gate in the charge storage transistor as would be conventional for speed improvement, the invention inverts the approach by placing the high-k metal gate only in the selection transistor. This inversion allows the charge storage transistor to maintain its charge storage capability while the selection transistor provides the speed benefit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the charge storage capacity of non-volatile memory and prevents charge trapping, enabling increased storage capability and faster processing speeds while maintaining reduced operation voltage.
Implementation Method 1
the charge storage structure includes a charge trapping layer
Data Source
AI summary
The invention provides a non-volatile memory and a fabricating method thereof. The non-volatile memory includes a substrate, an embedded-type charge storage transistor, and a selection transistor. The substrate has an opening. The embedded-type charge storage transistor is disposed in the substrate. The embedded-type charge storage transistor includes a charge storage structure and a conductive layer. The charge storage structure is disposed on the substrate in the opening. The conductive layer is disposed on the charge storage structure and fills the opening. The selection transistor is disposed on the substrate at one side of the embedded-type charge storage transistor, wherein the selection transistor includes a metal gate structure. The non-volatile memory has excellent charge storage capacity.