Embedded Semiconductor Chip Circuit Board Thermal Stress Balance
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Solution Overview
Problem
Traditional semiconductor packages face issues with asymmetry in circuit board structure, leading to unbalanced thermal stress, warpage, and increased production costs due to the embedding of semiconductor chips, which results in potential chip damage and inefficiencies in high-frequency operations.
Innovation Solution
A circuit board structure with an embedded semiconductor chip is developed, featuring a carrier board with through holes, photosensitive dielectric layers, and conductive connections, along with additional dielectric layers to balance thermal stress and prevent warpage, and a method for fabricating this structure that includes forming dielectric layers and a circuit layer to secure the chip and enhance thermal stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the circuit board structure is made asymmetric to embed semiconductor chip, then the electrical performance is improved, but the thermal stress becomes unbalanced causing warpage
Solution Approach 1:
The patent applies asymmetry by forming a circuit build-up structure on only one surface of the carrier board, which enables direct electrical connection between the semiconductor chip and external devices. This asymmetric design reduces the length of electrical transmission pathway and improves electrical performance while maintaining the embedded chip configuration.
Solution Approach 2:
The patent uses a compensation layer formed on the opposite surface of the carrier board to counterbalance the thermal stress caused by the asymmetric circuit build-up structure. This compensation layer acts as a counterweight that balances the thermal stress distribution, preventing warpage and maintaining structural stability during temperature variations.
2Device complexity
If the circuit build up structure is formed on single surface, then the electrical connection is simplified, but the thermal stress becomes unbalanced
Solution Approach 1:
The circuit build-up structure is formed asymmetrically on only one surface of the carrier board, simplifying the circuit structure and reducing manufacturing complexity. This asymmetric configuration allows direct electrical connection between the chip electrodes and external terminals without requiring complex through-hole wiring on both surfaces.
Solution Approach 2:
A compensation layer is formed on the opposite surface of the carrier board to counterbalance the thermal stress generated by the asymmetric circuit build-up structure. This compensation layer provides counterbalancing thermal mass that prevents unbalanced thermal stress and resulting warpage during temperature cycles.
3Length of moving object
If the semiconductor chip is embedded in the carrier board, then the connection path is shortened, but the warpage and chip damage risk increases
Solution Approach 1:
The semiconductor chip is embedded within a cavity formed in the carrier board, with the chip nested inside the carrier board structure. This nesting configuration shortens the electrical connection path between the chip and external terminals while providing mechanical protection for the chip.
Solution Approach 2:
A compensation layer is formed on the surface of the carrier board opposite to where the circuit build-up structure is located. This compensation layer counterbalances the thermal stress caused by the embedded chip configuration, preventing warpage that could lead to chip damage while maintaining the shortened connection path benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents warpage and chip damage by balancing thermal stress and reducing production costs, ensuring stable high-speed operation and improved electrical performance.
Implementation Method 1
at least one first dielectric layer made of a photosensitive material, formed on the first surface of the carrier board, and formed with an opening to expose the non-active surface of the semiconductor chip; at least one second dielectric layer made of a photosensitive material
Data Source
AI summary
The present invention provides a circuit board structure with an embedded semiconductor chip and a method for fabricating the same. The circuit board structure includes a carrier board having a first surface, a second surface, and a through hole penetrating the carrier board from the first surface to the second surface; a semiconductor chip having an active surface whereon a plurality of electrode pads are formed and a non-active surface, embedded in the through hole; a photosensitive first dielectric layer formed on the first surface of the carrier board and an opening formed thereon to expose the non-active surface of the semiconductor chip; a photosensitive second dielectric layer formed on the second surface of the carrier board and the active surface of the semiconductor chip.