Embedded Semiconductor Chip Package Structure for Layout Area Expansion
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Solution Overview
Problem
Conventional semiconductor package structures face issues such as reduced inner wiring layout area, high manufacturing costs, poor quality, and low yield rates due to the use of copper windows and CO2 laser processes, which result in inaccurate chip positioning and electrical connections.
Innovation Solution
A package structure is developed with two layers of wirings and an opening on a second insulating layer, eliminating the need for a core board and reducing size, while using a single lamination process to securely position electronic components without displacement, and forming openings using a grinding or laser process for improved electrical performance and signal stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a copper window is used as a blocking layer in the core board, then electromagnetic interference is blocked, but the inner wiring layout area is reduced
Solution Approach 1:
The invention extracts and removes the copper window blocking layer from the core board structure. Instead of using a copper window, the patent employs an embedded semiconductor chip approach where the chip itself serves as the electromagnetic shield while eliminating the need for separate copper blocking layers, thereby increasing the available wiring layout area
Solution Approach 2:
The semiconductor chip serves multiple functions simultaneously: it acts as both the functional electronic component and the electromagnetic interference blocking layer. This multi-functionality eliminates the need for separate copper windows while maintaining EMI protection and maximizing layout space
2Manufacturing precision
If a CO2 laser process is used to form the opening, then the opening can be formed precisely, but the manufacturing cost increases and organic fiberglass is exposed
Solution Approach 1:
The invention replaces expensive CO2 laser processing with more economical manufacturing methods. The patent uses standard PCB fabrication techniques including photolithography and etching to form openings and patterns, which are cheaper and more suitable for mass production while achieving sufficient precision
Solution Approach 2:
The invention changes the manufacturing parameters and methods from high-precision laser processing to conventional PCB fabrication techniques. By adjusting the approach to use standard industry processes with appropriate tolerances, the patent reduces manufacturing costs while maintaining adequate opening precision for chip embedding
3Reliability
If two dielectric materials are laminated to form the dielectric layer, then the chip is encapsulated, but the manufacturing time and cost increase and chip displacement occurs
Solution Approach 1:
The invention merges the encapsulation function into a single integrated dielectric layer structure rather than using two separate laminated dielectric materials. This consolidation reduces the number of manufacturing steps, decreases production time, and eliminates the risk of chip displacement that occurs during multiple lamination and curing processes
Solution Approach 2:
The patent segments the manufacturing process to form a single dielectric layer that simultaneously provides encapsulation and structural support functions. By integrating these functions into one layer formed in a single process step, the invention avoids the time-consuming sequential lamination of multiple dielectric layers
4Strength
If PI adhesive tapes are used to secure the chip, then the chip is attached to the carrier board, but the overall cost increases
Solution Approach 1:
The invention extracts and eliminates the PI adhesive tape from the manufacturing process. Instead of using separate adhesive tapes to secure the chip, the patent employs direct embedding of the chip into the dielectric layer with electrical connection through conductive pillars, removing the need for additional adhesive materials and associated costs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases layout usage rate, reduces size, enhances electrical performance, and stabilizes signals by allowing precise electronic component placement and reducing manufacturing time and costs.
Implementation Method 1
as the opening 130 is formed by a CO2 laser process
Implementation Method 2
forming openings using a grinding or laser process
Implementation Method 3
forming openings using a grinding or laser process
Data Source
AI summary
A method of manufacturing a package structure is provided, including forming a first wiring layer on a carrier board, forming up plurality of first conductors on the first wiring layer, forming a first insulating layer that encapsulates the first wiring layer and the first conductors, forming a second wiring layer on the first insulating layer, forming a plurality of second conductors on the second wiring layer, forming a second insulating layer that encapsulates the second wiring layer and the second conductors, and forming at least an opening on the second insulating layer for at least one electronic component to be disposed therein. Since the first and second insulating layers are formed before the opening, there is no need of stacking or laminating a substrate that already has an opening, and the electronic component will not be laminated and make a displacement. Therefore, the package structure thus manufactured has a high yield rate. The present invention further provides the package structure.