Embedded Chip Substrate Fabrication Using Recessed Nesting
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Solution Overview
Problem
The increasing number of electronic elements in electronic products leads to an expansion of circuit board area, hindering miniaturization, as traditional chip packages occupy valuable space on the board.
Innovation Solution
A fabrication method for an embedded chip substrate involves a core layer with an opening, insulation, and conductive layers, where a chip is embedded within a recess formed by these layers, allowing the chip to be electrically connected without occupying the circuit board's carrying area, using a lamination process with two-stage curable compounds to prevent air and moisture ingress and the 'popcorn effect'.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of electronic elements is increased to improve product functionality, then the carrying area on the circuit board must be extended, but this increases the area occupied by the circuit board, which deteriorates miniaturization of electronic products
Solution Approach 1:
The patent transitions from a two-dimensional surface mounting approach to a three-dimensional embedded structure. By embedding the chip vertically within the circuit board through a recess, the design utilizes the Z-dimension (depth) to accommodate electronic components, thereby reducing the horizontal footprint on the circuit board surface while maintaining component functionality.
Solution Approach 2:
The chip is nested within a recess formed in the circuit board structure. The embedding process creates a hierarchical arrangement where the chip is contained within the circuit board body, similar to nested dolls, maximizing space utilization and reducing the overall external dimensions of the electronic product.
2Quantity of substance
If traditional chip packages are used to carry electronic elements, then the carrying capacity is sufficient, but the occupied space on the circuit board increases, hindering miniaturization
Solution Approach 1:
Instead of expanding horizontally to accommodate more chips, the invention embeds chips vertically within the circuit board thickness. This dimensional shift allows multiple chips to be integrated within the same footprint area by utilizing the depth dimension, thereby maintaining carrying capacity while minimizing occupied surface area.
3Reliability
If a chip is embedded into the circuit board using insulation and conductive layers, then the chip integration is secure and airtight preventing the popcorn effect, but the fabrication process becomes more complex
Solution Approach 1:
The recess is formed in the core layer before the chip is embedded, and insulation layers are applied in advance to create a prepared embedding environment. This preliminary structuring ensures proper positioning and secure integration of the chip, preventing defects such as the popcorn effect while maintaining a systematic fabrication flow.
Solution Approach 2:
The embedding structure utilizes composite material layers including core layer, first insulation layer, first conductive layer, second insulation layer, and second conductive layer. These multi-material layers work together to provide mechanical support, electrical insulation, electrical connection, and hermetic sealing, achieving reliable and airtight chip integration.
Data Source
AI summary
An embedded chip substrate includes a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit layer. The core layer disposed on the first insulation layer has an opening that exposes a portion of the first insulation layer. The chip is adhered into a recess constructed by the opening and the first insulation layer. The second insulation layer is disposed on the core layer for covering the chip. The first circuit layer is disposed at the outer side of the first insulation layer located between the first circuit layer and the core layer. The second circuit layer is disposed at the outer side of the second insulation layer located between the second circuit layer and the core layer. The first circuit layer is electrically connected to the second circuit layer that is electrically connected to the chip.