Embedded Circuit Board Traces Structural Integrity
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Solution Overview
Problem
The manufacturing cost of circuit boards is high due to low yield rates, which is a significant challenge in the production of portable electronics, as existing methods do not effectively assess the quality of circuit layers before subsequent processing steps, leading to material wastage and reduced structural strength.
Innovation Solution
A method involving an automatic optical inspection (AOI) after forming the circuit layer to determine if subsequent processes can proceed, combined with embedding the circuit layer in a dielectric layer with specific surface configurations to enhance structural strength and prevent material separation, and an earlier etching process to solidly integrate the traces within the dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the circuit layer is embedded in the dielectric layer with conventional embedding methods, then the manufacturing process is simple, but the structural strength is insufficient and trace separation occurs
Solution Approach 1:
The patent applies preliminary action by forming a reinforcement structure (such as a rib or protrusion) on the circuit layer before embedding it in the dielectric layer. This pre-formed reinforcement structure prevents trace separation and enhances structural strength during subsequent processing, eliminating the need for complex post-processing reinforcement methods.
Solution Approach 2:
The patent uses composite materials by combining the circuit layer with a reinforcement structure (such as a rib made from the same or different material) and embedding this composite structure in the dielectric layer. This creates a multi-component system that provides both electrical functionality and enhanced mechanical strength, preventing trace separation while maintaining manufacturability.
2Reliability
If AOI is performed after all processing steps, then the inspection is comprehensive, but material wastage increases and manufacturing cost rises
Solution Approach 1:
The patent applies preliminary action by performing AOI inspection at an early stage in the manufacturing process, specifically after the circuit layer is formed but before embedding in the dielectric layer and subsequent processing steps. This early inspection identifies defects while materials can still be salvaged or reworked, preventing material wastage and reducing manufacturing costs while maintaining comprehensive circuit integrity verification.
Solution Approach 2:
The patent uses feedback by implementing AOI inspection that provides real-time information about circuit layer quality. This feedback mechanism allows for immediate identification and correction of defects, enabling process adjustments that prevent material wastage in subsequent embedding and processing steps, thereby reducing overall manufacturing costs while ensuring circuit integrity.
3Reliability
If the trace area is enlarged to improve connection, then the electrical connection is better, but the yield rate decreases due to increased material wastage
Solution Approach 1:
The patent uses composite materials by combining the circuit layer with a reinforcement structure (such as a rib) that provides both mechanical support and electrical connection functionality. This composite approach allows for optimized trace dimensions that balance electrical connection requirements with material usage efficiency, improving yield rate while maintaining reliable electrical connections through the multi-component structure.
Data Source
AI summary
A circuit board is disposed on a substrate and includes a dielectric layer and a circuit layer. The dielectric layer is disposed on the substrate. The circuit layer is embedded in the dielectric layer and has plural traces. Each of the traces has a first top surface and a first bottom surface which are opposite to each other, and the first bottom surface faces toward the substrate. The first top surface is exposed from the dielectric layer, and an area of a vertical projection of the first top surface on the substrate is smaller than an area of a vertical projection of the first bottom surface on the substrate.