Embedded Circuit Substrate for High I/O Density

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Solution Overview

Problem

The challenge in manufacturing semiconductor packages with increased I/O connections is the difficulty in maintaining a high bonding pad density without increasing the size of semiconductor chips, leading to issues such as imprecise line widths, peeling of traces, and uneven thickness of circuit layers, which affects electrical signal transmission and yield rates.

Innovation Solution

The use of a substrate with a first dielectric structure, a first circuit layer embedded within, and a second dielectric structure on top, where the second circuit layer is formed by electrolytic etching and embedded in the second dielectric structure, allowing for precise pattern design and fine I/O pitch without excess material removal, thus enhancing I/O connections and reducing the risk of peeling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If bonding pad density is increased to accommodate more I/O connections, then the number of I/O connections increases, but the size of semiconductor chips increases

Engineering Contradiction:

Improvenumber of I/O connectionsVSAvoidsize of semiconductor chips

Core Design Contradiction:

Quantity of substanceVSArea of moving object

Solution Approach 1:

The patent transitions from a single-layer circuit design to a multi-layer embedded circuit architecture. Circuit traces are embedded within dielectric layers rather than being confined to the surface, utilizing the third dimension (depth) to increase I/O connection density without expanding chip footprint. Multiple circuit layers at different depths provide additional routing pathways.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nested circuit layers where second circuit layers are embedded within dielectric structures that are themselves positioned on first circuit layers. This nested arrangement allows circuit traces to be embedded within the substrate structure, maximizing space utilization and enabling higher I/O density without increasing surface area.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Ease of manufacture

If conventional circuit layer formation methods are used, then manufacturing is simpler, but line widths are imprecise and traces peel

Engineering Contradiction:

Improvesimplicity of circuit layer formationVSAvoidline width precision

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies preliminary protective actions by embedding circuit layers within dielectric structures before subsequent processing steps. The dielectric material is deposited over the circuit traces, protecting them from mechanical stress and preventing peeling during later manufacturing operations. This preliminary embedding secures the traces in place.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent replaces conventional mechanical trace attachment methods with an electrolytic etching process. Instead of mechanically bonding or adhesion-dependent trace formation, the circuit layers are formed through electrochemical deposition and etching, providing precise control over line widths and eliminating mechanical peeling issues.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Measurement precision

If excess material is removed during circuit layer formation, then pattern definition is achieved, but the circuit layer becomes uneven in thickness

Engineering Contradiction:

Improvepattern definition accuracyVSAvoidcircuit layer thickness uniformity

Core Design Contradiction:

Measurement precisionVSManufacturing precision

Solution Approach 1:

The patent changes the formation parameters of the circuit layer by using electrolytic etching instead of conventional subtractive methods. The electrolytic process allows precise control of material removal through electrical parameters (current density, etching time, electrolyte composition), enabling accurate pattern definition while maintaining uniform thickness by controlling the etching rate across the entire surface.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables a higher I/O count and flexibility in trace routing while preventing peeling and ensuring reliable electrical signal transmission by maintaining a precise and thin second circuit layer, improving the yield rate and reducing manufacturing costs.

Implementation Method 1

electrolytic etching the conductive material on the first surface of the second dielectric structure to form a second circuit layer embedded in the second dielectric structure

Methodology Applied

Scientific EffectElectrolytic etching: Electrolysis

Data Source

PatentUS10096542B2Substrate, semiconductor package structure and manufacturing process

Publication Date: 2018.10.09 ADVANCED SEMICON ENG INC

AI summary

A substrate includes a first dielectric structure, a first circuit layer, a second dielectric structure and a second circuit layer. The first circuit layer is embedded in the first dielectric structure, and does not protrude from a first surface of the first dielectric structure. The second dielectric structure is disposed on the first surface of the first dielectric structure. The second circuit layer is embedded in the second dielectric structure, and is electrically connected to the first circuit layer. A first surface of the second circuit layer is substantially coplanar with a first surface of the second dielectric structure, and a surface roughness value of a first surface of the first circuit layer is different from a surface roughness value of the first surface of the second circuit layer.