Embedded Component Array in Fan-Out Packaging for VRM Footprint Reduction

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Solution Overview

Problem

High-power Voltage Regulator Modules (VRMs) face challenges in compact design due to the need for substantial capacitance, inductance, and resistance to produce clean low-voltage DC power at high currents, making it difficult to incorporate a large number of lumped elements in a small form factor.

Innovation Solution

The implementation of an embedded component array layer with Integrated Fanout (InFO) layers and connectivity layers, along with conductors providing signal routing, allows for the integration of passive devices within a Printed Circuit Board (PCB) core, reducing the need for surface-mounted components and enabling efficient power conversion in a compact footprint.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a large number of lumped elements are used to provide substantial capacitance, inductance, and resistance, then the VRM can produce clean low-voltage DC power at high currents, but the device footprint increases significantly

Engineering Contradiction:
Improvepower qualityVSAvoiddevice footprint
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges multiple discrete lumped elements (capacitors, inductors, resistors) into an integrated array structure where multiple passive devices are combined within a single packaged device. This consolidation reduces the overall device footprint while maintaining the necessary power conditioning capabilities for clean DC output.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from a two-dimensional surface-mounted arrangement of lumped elements to a three-dimensional integrated structure with multiple layers and stacked components. This dimensional change allows substantially more passive devices to be packed into a smaller footprint by utilizing vertical space and multiple packaging layers.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Area of stationary object

If the VRM is designed with a small form factor to meet space constraints, then the device footprint is reduced, but it becomes difficult to include the necessary lumped elements for power conditioning

Engineering Contradiction:
Improvedevice footprintVSAvoidcomponent integration
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent employs a nested structure where multiple passive devices are embedded within a packaged device core, with InFO layers and connectivity layers nested around and between the passive device arrays. This nesting allows multiple functional components to be contained within a compact hierarchical structure, achieving high component density in a small footprint.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent segments the VRM into distinct functional layers including imbedded component array layers, InFO layers, and connectivity layers. Each layer is optimized for its specific function, allowing independent design and optimization while maintaining overall system integration. This segmentation enables complex functionality to be achieved through modular layering rather than monolithic design.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11122678B2Packaged device having imbedded array of components
Publication Date: 2021.09.14 TESLA INC
  • US11122678B2 patent drawing
  • US11122678B2 patent drawing
  • US11122678B2 patent drawing

AI summary

A structure having imbedded array of components is described. An example structure includes an imbedded component array layer having an array of imbedded passive devices contained therein. The structure further includes an Integrated Fan-Out (InFO) layer residing adjacent a first surface of the imbedded component array layer having traces and vias formed therein. The structure further includes an insulator layer residing adjacent a second surface of the imbedded component array layer and electrically coupled to at least the InFO layer and vias passing through the imbedded component array layer and electrically coupled to some of vias of the InFO layer.