Embedded Conductive Elements in PCB Dielectric Layers

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Solution Overview

Problem

Conventional methods for manufacturing multilayer printed circuit boards face challenges in achieving reliable and consistent interconnections due to the complexity of microvia formation, which requires precise chemical processes and specialized equipment, and often result in wasted space and material inefficiency.

Innovation Solution

A method involving a single press lamination process using a dielectric layer with embedded glass cloth reinforcement, where electrically conductive elements are formed over a conductive pattern and then exposed through mechanical means, allowing for varied shapes and sizes without the need for uniform height or conical shapes, thus enabling efficient use of substrate space.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If conventional plated through-holes are used for interconnections, then electrical connections between layers are achieved, but valuable board space is wasted due to large via hole sizes and capture pads

Engineering Contradiction:

Improveboard spaceVSAvoidvia hole size control

Core Design Contradiction:

Area of stationary objectVSManufacturing precision

Solution Approach 1:

The patent changes the size parameter of interconnection elements from conventional large plated through-holes to small embedded conductive elements, reducing the area occupied by interconnections and increasing usable board space

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent transitions from surface-level plated through-holes to embedded conductive elements within the dielectric layer, utilizing the third dimension (depth) to achieve higher interconnection density without increasing surface area

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Area of stationary object

If microvias are formed using laser, photolithography and plasma etching, then smaller opening interconnections are achieved, but the process requires tight process control and sophisticated equipment to ensure reliability and consistency

Engineering Contradiction:

Improvevia opening sizeVSAvoidmanufacturing process complexity

Core Design Contradiction:

Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent extracts the conductive elements from the complex multi-step microvia formation process and embeds them directly into the dielectric layer during lamination, eliminating the need for laser drilling, plasma etching, and multiple chemical treatment steps

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent uses standard, readily available materials and processes (lamination, mechanical means) instead of expensive specialized equipment and materials required for microvia formation, making the process more accessible and cost-effective

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

3Reliability

If electroless copper deposition and electrolytic copper plating are used to seed microvia walls, then conductive pathways are formed, but multiple chemical processes with rinses are required, increasing process complexity and potential for defects

Engineering Contradiction:

Improveconductive pathway reliabilityVSAvoidchemical process steps

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the functions of multiple chemical deposition processes into a single embedding step during dielectric lamination, where conductive elements are placed and embedded in one operation rather than through sequential chemical treatments

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent replaces complex chemical processes (electroless deposition, electrolytic plating) with mechanical embedding during lamination, using physical pressure and heat to embed conductive elements rather than chemical reactions to form conductive pathways

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

4Area of stationary object

If vertical interconnection is implemented to save space, then board space efficiency improves, but the manufacturing process requires precise control of conductive element height and shape

Engineering Contradiction:

Improveusable board areaVSAvoidconductive element uniformity

Core Design Contradiction:

Area of stationary objectVSManufacturing precision

Solution Approach 1:

The patent allows conductive elements to protrude beyond the dielectric layer surface during embedding, then trims them to the required height, rather than attempting to achieve precise height control during the embedding process itself. This partial action approach (embed first, trim later) simplifies the manufacturing process

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS7631423B2Method and process for embedding electrically conductive elements in a dielectric layer

Publication Date: 2009.12.15 SANMINA CORP

AI summary

A method is provided for fabricating a multilayer printed circuit board, including embedded electrically conductive elements formed as part of the fabrication of the layers of the printed circuit board. An insulating layer and a conductive layer are then pressed over the electrically conductive elements such that the electrically conductive elements protrude from the surface of the conductive layer. A mechanical process is the applied to remove these protrusions to expose the embedded electrically conductive elements. An electrically conductive undercoat may be applied over the surface of the conductive layer and a second circuit pattern is formed over the electrically conductive undercoat.