Embedded Conductive Traces in Semiconductor Base for Thermal Management
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Solution Overview
Problem
Flip-chip semiconductor packages face thermal electrical issues such as heat dissipation, cross talk, and electromagnetic interference due to increased input/output connections, which affect the reliability and quality of electronic products.
Innovation Solution
A semiconductor package with conductive traces embedded in a base, such as a printed circuit board, where the semiconductor device is mounted using conductive structures like copper pillar bumps or wire bonding, and additional insulation material is applied to manage signal routing and reduce thermal electrical problems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If flip-chip technology with area array is used to achieve high density interconnection, then interconnection density is improved, but thermal electrical problems such as heat dissipation and electromagnetic interference worsen
Solution Approach 1:
The patent transitions from planar 2D trace routing to 3D embedded traces within the substrate. Conductive traces are embedded within the substrate thickness, utilizing the vertical dimension to route signals. This dimensional change allows traces to be positioned optimally for thermal management and electromagnetic shielding, resolving the contradiction between high interconnection density and thermal electrical performance.
Solution Approach 2:
The substrate employs composite material construction with multiple layers including conductive traces embedded within insulating material layers. This composite structure enables simultaneous achievement of high interconnection density through conductive paths while maintaining thermal electrical performance through the insulating and thermally conductive properties of the composite substrate materials.
2Productivity
If line widths are minimized to support high-density connections, then interconnection density is improved, but manufacturing precision requirements worsen
Solution Approach 1:
By embedding traces in three dimensions within the substrate rather than routing them on the surface, the patent reduces the impact of minimal line width variations. The embedded configuration provides better mechanical support and control over trace geometry, lowering manufacturing precision requirements while maintaining high interconnection density.
3Reliability
If direct chip attach is used to reduce inductance, then interconnection performance is improved, but thermal electrical problem management becomes more difficult
Solution Approach 1:
The embedded trace substrate acts as an intermediary between the chip and the external environment. The conductive traces embedded within the substrate provide low-inductance paths for electrical connections while the substrate's thermal conductivity and structure facilitate heat dissipation away from the chip, resolving the contradiction between interconnection performance and thermal management.
Data Source
AI summary
The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.