Embedded Die Interconnect Structure for High-Density Die-to-Die Links
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Solution Overview
Problem
Conventional methods for integrating heterogeneous dies in integrated circuits impose limitations on interconnect density and functionality, limiting the effectiveness of die-to-die connections.
Innovation Solution
The integration of secondary dies into the interconnect layers of a base die, allowing for electrical connections through both top and bottom surfaces, and lateral connections within the interconnect structure, enhancing interconnect density and functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional methods for integrating heterogeneous dies are used, then the integration of different materials and technology nodes is achieved, but the interconnect density and functionality are limited
Solution Approach 1:
The patent embeds secondary dies within the interconnect layers of the base die, creating a nested structure where smaller functional blocks are integrated inside the three-dimensional space of the main die. This nesting approach dramatically increases interconnect density by utilizing the vertical dimension and internal space of the interconnect layers, rather than only surface-level integration
Solution Approach 2:
The invention transitions from conventional two-dimensional surface integration to three-dimensional embedding by placing secondary dies within the interconnect layers at different vertical levels. This dimensional change enables multiple layers of integration, allowing interconnect structures to extend both horizontally and vertically, thereby significantly increasing the quantity of interconnections without proportionally increasing the footprint area
2Quantity of substance
If secondary dies are embedded in interconnect layers, then interconnect density improves by orders of magnitude, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by preparing recesses in the interconnect layers before embedding the secondary dies. The recesses are formed with appropriate dimensions and electrical connection structures in advance, allowing the secondary dies to be precisely positioned and integrated. This preliminary preparation simplifies the overall manufacturing process by organizing complex steps into a systematic sequence
Solution Approach 2:
The integration process is divided into distinct segments: forming recesses in interconnect layers, preparing electrical connections, embedding secondary dies, and completing interconnect structures. This segmentation of the manufacturing process makes the complex task of high-density integration more manageable and manufacturable by breaking it into standardized, repeatable steps
3Adaptability or versatility
If multiple electrical connections are made through top and bottom surfaces, then functionality and communication efficiency improve, but device complexity increases
Solution Approach 1:
The embedded secondary dies serve multiple functions: they provide additional logic functionality, memory capacity, and specialized processing capabilities within the same interconnect structure. The interconnect layers themselves serve dual purposes by both connecting the base die circuits and housing the embedded secondary dies, thereby increasing versatility without proportionally increasing structural complexity
Data Source
AI summary
An integrated circuit includes a first die and a second die. The second die is embedded or otherwise contained in a layered interconnect structure of the first die. The second die can be an IC die or it can be an electrically inactive element, such as a heat spreader. A portion of the layered interconnect structure is laterally adjacent to the second die. A first part of the second die can be electrically connected to a second part of the second die via the interconnect structure of the first die. The second die can be operatively coupled to the first die using electrical connections between the second die and one or more interconnect layers above or below the second die, or to devices of the first die. A method of fabricating an interconnect structure with one or more embedded dies is also disclosed.