Embedded Die Package Coplanar Metal Heat Dissipation
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Solution Overview
Problem
Current chip packaging technologies, such as Fan Out Wafer Layer Packaging (FOWLP) and panel-based embedded die technologies, face limitations in cost, performance, and heat dissipation due to complex manufacturing processes, alignment challenges, and the need for precise via creation, which restricts the number of chips that can be processed and increases unit costs.
Innovation Solution
The proposed embedded chip package design features a die surrounded by a frame with a polymer matrix, where both the die and frame surfaces are coplanar, allowing direct metal layer attachment for improved heat dissipation and electrical connectivity, with a copper layer serving as a heat sink and redistribution layer, enabling efficient heat management and reduced manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FOWLP is used to embed chips on wafer, then chip embedding is achieved with electrical connectivity, but the number of chips that can be processed is limited due to wafer size constraints
Solution Approach 1:
The invention segments the packaging process into two independent stages: first fabricating chips on standard wafers, then transferring and embedding them into larger panel substrates. This allows the chip fabrication to occur on manageable wafer sizes while the final packaging benefits from the larger panel area, effectively resolving the contradiction between wafer size limitations and the need to process more chips.
Solution Approach 2:
The invention transitions from two-dimensional wafer-based processing to three-dimensional panel-based embedding. By standing the wafer on its edge during transfer and embedding chips vertically into the panel substrate, the system utilizes the third dimension (depth/height) to accommodate more chips in a given footprint area, thereby increasing productivity without being constrained by wafer diameter.
2Productivity
If panel-based embedding is used to increase chip capacity, then more chips can be processed, but manufacturing complexity increases due to alignment and via creation challenges
Solution Approach 1:
The invention performs preliminary actions by pre-fabricating chips on wafers with their metal interconnect layers already formed, and pre-preparing panel substrates with through-holes and conductive vias before chip transfer. This preliminary preparation simplifies the subsequent embedding process, as chips can be directly transferred and connected without requiring complex real-time alignment and via creation operations during the main packaging process.
Solution Approach 2:
The invention introduces an intermediary transfer process using tape automation and bonding techniques that mediate between wafer fabrication and final panel embedding. The tape serves as a temporary carrier that holds chips in array format, enabling easy transfer to the panel substrate while maintaining alignment. This intermediary step decouples the complexity of precise alignment and via formation from the main embedding process, reducing overall manufacturing complexity.
3Reliability
If dielectric layers are added to protect terminals and enable via formation, then chip embedding is achieved, but manufacturing cost and process complexity increase
Solution Approach 1:
The invention makes the substrate panel serve multiple functions simultaneously: it provides mechanical support for the embedded chips, contains the conductive vias for electrical connectivity, and offers a planar surface for mounting. By integrating these functions into a single substrate structure rather than requiring separate dielectric protection layers and via formation steps, the manufacturing process is simplified and costs are reduced while maintaining embedding reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances heat dissipation, reduces manufacturing costs, and increases the number of chips that can be processed per unit area, making it suitable for high-performance applications while maintaining competitive pricing.
Implementation Method 1
a second metal layer is directly attached to the die back face, second frame face and packaging and extends in a layer that is at least 1 micron thick over the frame surface and at least 4 micron meters thick over the die and packaging material surfaces
Implementation Method 2
a second metal layer is directly attached to the die back face... and at least 4 micron meters thick over the die and packaging material surfaces
Implementation Method 3
a first metal layer that is at least 1 micron thick and that is directly attached to the die, packaging material and first frame surface, and wherein a second metal layer is directly attached to the die back face
Data Source
AI summary
A structure consisting of at least one die embedded in a polymer matrix and surrounded by the matrix, and further consisting of at least one through via through the polymer matrix around perimeter of the die, wherein typically the at least one via has both ends exposed and where the die is surrounded by a frame of a first polymer matrix and the at least one through via passes through the frame; the die is positioned with terminals on a lower surface such that the lower surface of the chip is coplanar with a lower surface of the frame, the frame is thicker than the chip, and metal is directly attached to and covers at least part of the upper surface of the chip.