Embedded Die Panel Structure Without Interposers
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Solution Overview
Problem
Conventional semiconductor packaging methods face limitations in efficiently embedding integrated circuit dies without the need for interposers, while also providing effective thermal management and electrical connectivity.
Innovation Solution
The method involves forming layered structures with redistribution layers and dielectric layers, creating vias, and embedding semiconductor dies in a panel structure using copper pillars for electrical coupling, without the use of interposers, and utilizing ablation and adhesive layers for structural support and electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor packaging methods are used with interposers, then electrical connectivity and thermal management are achieved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent removes the interposer component from the packaging structure entirely. Instead of using an interposer to provide electrical connectivity between dies, the invention directly couples dies to the substrate using redistribution layers and vias, thereby eliminating the intermediate component while maintaining connectivity functionality.
Solution Approach 2:
The substrate is designed to perform multiple functions: it serves as both the mechanical support platform and the electrical interconnection medium. The redistribution layers on the substrate provide both structural organization and electrical routing, replacing the specialized interposer's functionality with integrated substrate design.
2Temperature
If conventional semiconductor packaging methods are used with interposers, then thermal management is achieved, but manufacturing cost and cycle time increase
Solution Approach 1:
The interposer component responsible for thermal management is removed. Thermal conduction paths are instead created through direct material contact between dies, substrate, and thermal interface materials, eliminating the need for expensive interposer materials and their associated manufacturing processes.
Solution Approach 2:
The thermal management function is merged into the substrate and die assembly process. The substrate serves dual purposes as both structural support and thermal conduction path, while the adhesive layers used for die attachment also provide thermal interface functionality, consolidating multiple functions into fewer components.
3Reliability
If conventional semiconductor packaging methods are used, then die embedding is achieved, but processing density and efficiency are limited
Solution Approach 1:
The packaging process is segmented into modular steps: die attachment to substrate, formation of redistribution layers, via creation, and encapsulation. This modular approach allows each step to be optimized independently and enables parallel processing of multiple dies, increasing overall production density and efficiency.
Solution Approach 2:
The patent transitions from planar die arrangement to three-dimensional embedded structures with multiple redistribution layers at different heights. This vertical dimensionality allows higher processing density by stacking functional layers rather than spreading them out horizontally, enabling more compact and efficient packaging.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the efficient embedding of semiconductor dies in a panel structure, providing enhanced thermal management and electrical connectivity, while reducing manufacturing costs and cycle times, and allowing for high-density processing of embedded die structures.
Implementation Method 1
The second layered structure may be bonded to the first layered structure utilizing an adhesive layer
Implementation Method 2
The first, second, and third dielectric layers may be ablated to form the vias and second and third redistribution layers
Data Source
AI summary
Methods for an embedded die panel are disclosed and may include fabricating a first layered structure by: forming first redistribution layers on a first carrier, forming a first dielectric layer on the first redistribution layers and carrier, forming a mask pattern on the first dielectric layer exposing a portion of the first dielectric layer, forming a second dielectric layer on the exposed portion of the first dielectric layer, forming vias in the first and second dielectric layers, and forming second redistribution layers on the second dielectric layer. The mask pattern may be removed forming a die cavity defined by the second dielectric layer. A second layered structure coupled to the first layered structure may be formed comprising a second carrier, a third dielectric layer, third and fourth redistribution layers on opposite surfaces of the third dielectric layer, and a semiconductor die.