Embedded Dielectric Isolation for MOS Leakage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
MOS transistors in integrated circuits face issues with internal leakage between the source and drain, leading to increased parasitic capacitance and the floating body effect, which hinder device miniaturization and efficiency.
Innovation Solution
An embedded dielectric structure is introduced beneath the active portions of the MOS device, including the source and drain extensions and channel region, to reduce channel leakage and parasitic capacitance while avoiding the floating body effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device size is reduced to increase chips per substrate, then productivity is improved, but internal leakage between source and drain increases
Solution Approach 1:
An embedded dielectric structure is introduced as an intermediary element between the source and drain regions. This dielectric layer acts as a mediator that electrically isolates the source and drain, preventing carrier leakage while maintaining the reduced device dimensions needed for high-density integration.
Solution Approach 2:
The dielectric structure is selectively embedded only in specific regions where leakage occurs (between source and drain), rather than uniformly throughout the entire device. This localized approach reduces leakage where needed while preserving the electrical connectivity and performance in other critical regions.
2Length of moving object
If source and drain are brought closer to reduce channel length, then device size is reduced, but drain-induced barrier lowering increases
Solution Approach 1:
The embedded dielectric structure serves as an intermediary that modifies the electric field distribution between the source and drain. By introducing this dielectric layer, the harmful electric field coupling that causes DIBL is reduced, allowing short channel lengths to be maintained without suffering from severe DIBL effects.
3Length of moving object
If physical dimensions of source and drain are decreased, then device size is reduced, but parasitic capacitance with substrate increases
Solution Approach 1:
The embedded dielectric structure acts as an intermediary layer that reduces the parasitic capacitance between the source/drain regions and the substrate. By introducing this low-k dielectric material, the electric field coupling to the substrate is reduced, thereby lowering parasitic capacitance even as device dimensions are scaled down.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The embedded dielectric structure effectively reduces channel leakage current, lowers parasitic capacitance, and prevents the floating body effect, enhancing the performance and power efficiency of MOS devices.
Implementation Method 1
An embedded dielectric structure underlying an active portion of the device, such as a source extension or a drain extension
Implementation Method 2
The parasitic capacitances of the source and drain with the substrate also become increasingly important
Data Source
AI summary
An MOS device has an embedded dielectric structure underlying an active portion of the device, such as a source extension or a drain extension. In an alternative embodiment, an embedded dielectric structure underlies the channel region of a MOS device, as well as the source and drain extensions.