Embedded DRAM via placement using ferroelectric etch stop
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Solution Overview
Problem
Conventional DRAM devices face integration challenges with logic devices due to differences in critical dimensions and processes, leading to increased complexity, cost, and wasted area from topographic height differences, as well as electrical shorts from misalignment.
Innovation Solution
An embedded DRAM device with a high-k ferroelectric layer disposed over electrode layers of capacitors, extending along the interlayer dielectric layer, which acts as an etch stop and prevents electrical shorts, allowing for direct via placement without a top hat metal layer and minimizing z-height differences between memory and logic areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If a top hat metal layer is used directly on the COB, then the capacitor structure is formed, but a height difference is generated between memory and logic areas resulting in wasted area and transition region
Solution Approach 1:
The patent removes the top hat metal layer from the COB structure, extracting the problematic element that caused the height difference. Instead of using a top hat metal layer to cap the COB, the invention allows the via to land directly on the COB, eliminating the source of the topographic issue while maintaining electrical functionality.
Solution Approach 2:
The patent changes the vertical dimension of the COB structure by eliminating the top hat metal layer extension. This dimensional change flattens the memory area topography to match the logic area, eliminating the need for transition regions and maximizing usable area.
2Area of stationary object
If the top via is landed directly on the COB without top HAT metal layer, then the height difference is reduced, but a slight misalignment leads to electrical short between top via and bottom electrode
Solution Approach 1:
The patent introduces a new intermediary layer between the via and the COB bottom electrode. This intermediate structure provides a buffer zone that prevents direct electrical contact while maintaining mechanical support, thereby preventing shorts even when misalignment occurs.
Solution Approach 2:
The patent implements a protective intermediate layer in advance of potential misalignment issues. This cushioning layer is deposited beforehand to provide a safety margin that prevents electrical shorts before they can occur during device operation or testing.
3Shape
If separate lithographic and etching processes are used for metal layers in logic and COB memory areas, then the capacitor structure is formed, but process complexity and cost increase
Solution Approach 1:
The patent merges the processing of logic and memory areas into unified lithographic and etching processes. By eliminating the top hat metal layer, the invention allows both areas to be processed simultaneously using the same process steps, reducing complexity and cost.
Solution Approach 2:
The patent creates a universal processing approach that handles both logic and COB memory areas with the same lithographic and etching processes. This multi-functional process design eliminates the need for separate processing streams, reducing overall device complexity and manufacturing cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces the overall z-height of the DRAM device, simplifies integration, decreases costs, and provides denser, faster memory solutions by eliminating the need for deep COB trenches and preventing electrical shorts, while enabling direct via placement on the COB.
Implementation Method 1
an etch stop layer using a replacement COB integration technique
Implementation Method 2
a high-k ferroelectric layer disposed below an electrode layer of a capacitor
Data Source
AI summary
Embodiments include an embedded dynamic random access memory (DRAM) device, a method of forming an embedded DRAM device, and a memory device. An embedded DRAM device includes a dielectric having a logic area and a memory area, and a trace and a via disposed in the logic area of dielectric. The embedded DRAM device further includes ferroelectric capacitors disposed in the memory area of dielectric, where each ferroelectric capacitor includes a first electrode, a ferroelectric layer, and a second electrode, and where the ferroelectric layer surrounds the first electrode of each ferroelectric capacitor and extends along a top surface of the dielectric in the memory area. The embedded DRAM device includes an etch stop layer above the dielectric. The second etch stop in the logic area may have a z-height that is approximately equal to a z-height of a top surface of the second etch stop in the memory area.