Embedded Ferroelectric Transistors for Compact CMOS Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of ferroelectric field effect transistors (FeFETs) with CMOS devices in semiconductor manufacturing is hindered by complex routing and large footprints due to their placement in the back-end-of-line (BEOL) processes, where they lack direct contact with gate and source/drain vias, and are limited by thermal budgets that restrict the use of metals like copper.
Innovation Solution
Integrating FeFETs with MOSFETs in the middle-end-of-line (MEOL) processes, allowing direct contact with gate and source/drain vias, relaxing thermal budgets, and reducing the footprint by forming them before the BEOL process, thus enabling shorter and simpler routing and the use of higher temperatures for annealing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If FeFETs are integrated in the back-end-of-line (BEOL) processes, then CMOS device manufacturing can proceed with standard thermal budgets, but the FeFET footprint becomes large and routing becomes complex due to lack of direct contact with gate and source/drain vias
Solution Approach 1:
The FeFETs are formed in the middle-end-of-line (MEOL) process stage, before the back-end-of-line (BEOL) interconnect layers are deposited. This preliminary formation allows the FeFETs to be integrated into the CMOS structure while gate and source/drain vias are still accessible, enabling direct contact and simpler routing without requiring complex BEOL modifications
Solution Approach 2:
The patent transitions from vertical integration (stacking FeFETs above CMOS in BEOL) to lateral integration (forming FeFETs alongside CMOS devices in MEOL). This dimensional change allows direct contact with gate and source/drain vias through the substrate plane, reducing routing complexity while maintaining thermal budget constraints
2Temperature
If FeFETs are formed in the back-end-of-line (BEOL) processes, then thermal budget constraints are respected, but the FeFET footprint increases and requires more chip area
Solution Approach 1:
FeFETs are formed in the middle-end-of-line (MEOL) process stage, before back-end-of-line (BEOL) interconnect layers are deposited. This timing allows direct contact with gate and source/drain vias, reducing the required footprint by eliminating the need for extended routing structures that would be necessary if formed later in BEOL
3Ease of manufacture
If FeFETs are integrated in the back-end-of-line (BEOL) processes, then standard manufacturing processes can be used, but the routing becomes longer and more complex
Solution Approach 1:
The FeFETs are formed in the middle-end-of-line (MEOL) process stage, when gate and source/drain vias are still accessible. This preliminary formation enables direct contact between FeFET terminals and CMOS vias, significantly reducing routing length and complexity compared to forming FeFETs later in BEOL where such direct contact would not be possible
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in smaller FeFET footprints, simplified routing, and a relaxed thermal budget, allowing for more efficient integration and higher processing temperatures, enhancing the functionality and manufacturing efficiency of semiconductor devices.
Implementation Method 1
a ferroelectric layer (FE layer 134)
Data Source
AI summary
A method includes providing a structure having a substrate, gate stacks and source/drain (S/D) features over the substrate, S/D contacts over the S/D features, one or more dielectric layers over the gate stacks and the S/D contacts, and a via structure penetrating the one or more dielectric layers and electrically connecting to one of the gate stacks and the S/D contacts. The method further includes forming a ferroelectric (FE) stack over the structure, wherein the FE stack includes an FE layer and a top electrode layer over the FE layer, wherein the FE stack directly contacts the via structure; and patterning the FE stack, resulting in a patterned FE stack including a patterned FE feature and a patterned top electrode over the patterned FE feature.