Embedded FeRAM Cell With Select Gate for Low Unselected Current
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Solution Overview
Problem
Unwanted currents in channel regions of unselected 1T FeRAM cells increase power consumption and negatively impact read operations, particularly as the size of FeRAM cells decreases.
Innovation Solution
Incorporating a select gate that selectively provides access to the FeRAM device, operating as a 1.5 transistor FE RAM cell, which reduces current in channel regions of unselected cells by using gate voltages at multiple conductive electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a 1T FeRAM cell configuration is used, then device complexity is reduced and fabrication is simplified, but unwanted currents increase power consumption and negatively impact read operations
Solution Approach 1:
The invention segments the gate control function into two separate gates: a first gate that controls the channel region and a second gate that controls the ferroelectric layer. This segmentation allows independent control of charge injection and storage, enabling the reduction of unwanted currents in unselected cells while maintaining the simplified 1T cell structure.
Solution Approach 2:
The invention introduces a tunnel barrier layer as an intermediary between the first electrode and the ferroelectric layer. This tunnel barrier enables controlled charge injection through quantum tunneling mechanisms, allowing precise control over the charge stored in the ferroelectric layer while minimizing leakage currents in unselected cells.
2Productivity
If FeRAM cell size is decreased to increase density, then productivity is improved, but unwanted currents in channel regions increase power consumption
Solution Approach 1:
By segmenting the gate control into two separate gates, the invention enables independent optimization of charge control for each gate. This allows the use of higher voltage on the first gate for reliable charge injection even in scaled devices, while the second gate can be optimized to minimize leakage, thereby maintaining low power consumption at higher densities.
Solution Approach 2:
The invention changes the electrical parameters by applying different voltages to the two gates independently. The first gate can be biased at a higher voltage to ensure sufficient charge injection, while the second gate voltage can be adjusted to control the ferroelectric polarization state. This parameter differentiation allows scaled devices to maintain proper charge control without increased leakage currents.
3Loss of energy
If a select gate is added to reduce current in unselected cells, then power consumption is improved, but device complexity increases
Solution Approach 1:
The invention makes both gates multi-functional: the first gate serves as both a control gate for charge injection and as part of the read/write operation control, while the second gate serves as both a control gate for ferroelectric polarization and as a select mechanism. This multi-functionality eliminates the need for separate select transistors, reducing overall device complexity while achieving low power consumption.
Solution Approach 2:
The two-gate structure enables the FeRAM cell to self-select and self-control its operation. By independently controlling the two gates, the cell can autonomously control charge injection and storage without requiring external select transistors or additional control circuitry, thereby reducing device complexity while achieving selective access and low power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves power consumption and read operations of the FeRAM array by minimizing current in unselected cells, while allowing for a simpler and cost-effective fabrication process.
Implementation Method 1
The plurality of FeRAM cells respectively comprise a ferroelectric material able to store a data state depending upon charges accumulated within the channel region and/or a bias voltage applied to the conductive electrode
Implementation Method 2
The tunnel barrier layer is arranged between the first electrode and the ferroelectric layer
Data Source
AI summary
The present disclosure relates to an integrated chip structure. The integrated chip structure includes a first source/drain region and a second source/drain region disposed within a substrate. A select gate is disposed over the substrate between the first source/drain region and the second source/drain region. A ferroelectric random-access memory (FeRAM) device is disposed over the substrate between the select gate and the first source/drain region. A first sidewall spacer, including one or more dielectric materials, is arranged laterally between the select gate and the FeRAM device. An inter-level dielectric (ILD) structure laterally surrounds the FeRAM device and the select gate and vertically overlies a top surface of the first sidewall spacer.