Embedded FeRAM Cell Layout With Select Gate for Low-Leakage Reads
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Solution Overview
Problem
Ferroelectric random-access memory (FeRAM) devices experience unwanted currents in unselected 1T cells, leading to increased power consumption and negatively impacting read operations, especially as the size of these cells decreases.
Innovation Solution
Incorporating a select gate that selectively provides access to the FeRAM device, configuring it to operate as a 1.5 transistor cell, which reduces current in channel regions of unselected cells and improves power consumption and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 1T FeRAM cell size is reduced, then memory density increases, but unwanted currents in channel regions increase power consumption and negatively impact read operations
Solution Approach 1:
The patent introduces a select gate structure that segments the channel region of the FeRAM cell, creating a controlled access path. This segmentation allows the channel to be divided into regions that are selectively enabled or disabled, thereby reducing unwanted leakage currents in unselected cells while maintaining high memory density through the compact 1T cell design.
Solution Approach 2:
The select gate acts as an intermediary element between the control circuitry and the FeRAM cell array. By introducing this intermediate control structure, the patent enables selective activation of specific cell channels, thereby reducing power consumption from leakage currents in unselected cells without compromising the high-density 1T cell architecture.
2Quantity of substance
If 1T FeRAM cell size is reduced, then memory density increases, but read operations are negatively impacted due to unwanted currents
Solution Approach 1:
The select gate structure segments the bit line access paths to individual FeRAM cells, creating isolated channel regions that can be selectively activated. This segmentation prevents unwanted currents from interfering with read operations in selected cells, thereby improving read reliability while maintaining the high memory density of the 1T cell design.
Solution Approach 2:
The select gate serves as an intermediary control element that mediates between the bit lines and the FeRAM cell array. This intermediate structure enables clean separation of selected and unselected cell channels, eliminating unwanted current interference during read operations while preserving the compact high-density cell architecture.
3Loss of energy
If a select gate is added to create a 1.5T FeRAM cell, then power consumption is reduced and read operations improve, but device complexity increases
Solution Approach 1:
Instead of implementing a full 2T structure with two complete transistors per cell, the patent applies partial action by adding only the essential select gate element to the 1T cell. This partial enhancement provides the necessary channel control for reduced power consumption and improved read operations while avoiding the full complexity overhead of a complete 2T design, achieving an optimal 1.5T configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of a select gate in FeRAM cells effectively minimizes channel currents in unselected cells, enhancing power efficiency and read operations while allowing for a simpler fabrication process, thus reducing costs.
Implementation Method 1
Each of the plurality of FeRAM cells respectively comprises a ferroelectric material and a control electrode. A data state is written to a selected FeRAM device by applying a voltage across the selected FeRAM device that aligns electric dipoles in the ferroelectric material.
Implementation Method 2
A first conductive plateau in the transfer curve indicates a first data state stored in the selected FeRAM device, and a second conductive plateau in the transfer curve indicates a second data state stored in the selected FeRAM device.
Data Source
AI summary
The present disclosure relates to an integrated chip structure. The integrated chip structure includes a first source/drain region and a second source/drain region disposed within a substrate. A select gate is over the substrate between the first source/drain region and the second source/drain region. A ferroelectric random access memory (FeRAM) device is over the substrate between the select gate and the first source/drain region. A transistor device is disposed on an upper surface of the substrate. The substrate has a recessed surface that is below the upper surface of the substrate and that is laterally separated from the upper surface of the substrate by a boundary isolation structure extending into a trench within the upper surface of the substrate. The FeRAM device is arranged over the recessed surface.