3D Embedded Ferroelectric Memory Stacks for High-Bandwidth ICs

The patent transitions from planar 2D memory architecture to three-dimensional stacked architecture with multiple memory levels (Level 1, Level 2, etc.) vertically stacked above the substrate. This vertical stacking enables significantly higher memory density by utilizing the third dimension (height) rather than only expanding in the planar direction, directly resolving the contradiction between memory density and fabrication complexity.

The patent implements a nested structure where multiple memory levels are stacked vertically, with each level containing bit cells, word lines, and bit lines that are nested within the three-dimensional space. The Level 2 memory is positioned above Level 1 memory, creating a nested hierarchical structure that maximizes space utilization and achieves high density while maintaining organized fabrication processes.

The patent segments the memory system into multiple independent levels (Level 1, Level 2, etc.), each with its own array of bit cells, word lines, and bit lines. This segmentation allows parallel access to different memory levels, reducing the overall access time compared to a single large memory block. The segmented architecture enables simultaneous operations across levels, mitigating the latency increase that would otherwise result from stacking.

By organizing memory in vertical stacks with multiple levels accessed through three-dimensional interconnects, the patent enables short signal paths between memory cells and control circuitry. The vertical stacking with direct inter-level connections reduces the physical distance signals must travel compared to planar expansion, thereby reducing signal latency despite increased memory density.

The patent achieves high bandwidth by stacking multiple memory levels vertically and implementing three-dimensional interconnect structures that provide multiple parallel data paths between memory levels and control circuitry. This vertical architecture with multi-layer interconnects enables simultaneous data transfer across multiple levels, dramatically increasing bandwidth compared to planar expansion while using standard semiconductor fabrication processes.

The patent employs universal fabrication processes from the backend-of-line (BEOL) to create both the memory structures and interconnect layers. The same fabrication techniques used for planar interconnects are applied to create vertical vias and stacked structures, making the manufacturing process scalable and compatible with existing semiconductor manufacturing capabilities, thus maintaining ease of manufacture while achieving high bandwidth.

The patent implements vertical stacking with precise alignment between memory levels using backend-of-line fabrication processes that create vertically aligned vias and interconnect structures. The fabrication process utilizes sequential deposition and etching steps that inherently maintain vertical alignment, achieving the required manufacturing precision for stacked memory while enabling high density through the third dimension.

The patent employs planarization techniques and conformal deposition processes that create uniform, flat surfaces at each memory level, ensuring equipotential conditions for subsequent fabrication steps. This approach maintains consistent alignment and spacing between stacked levels, reducing the impact of surface variations and achieving the necessary manufacturing precision for vertical stacking.