Embedded Flash Memory Gate Stack for SOC Integration

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Solution Overview

Problem

The integration of flash memories with other types of devices on a System-On-Chip (SOC) faces challenges due to structural differences, particularly in managing varying power supply voltages and optimizing manufacturing processes for embedded memory devices.

Innovation Solution

The formation of embedded memory devices involves a gate-last or gate-first approach, utilizing a stack of dielectric layers including a charge trapping layer, high-k dielectric layer, and metal gates, which allows for optimized performance and reduced threshold voltage mismatch across different memory types on the same chip.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If flash memories are integrated with other circuit devices on the same chip, then system functionality and storage capacity are improved, but manufacturing complexity and process optimization difficulty increase due to structural differences

Engineering Contradiction:

Improveintegration capabilityVSAvoidmanufacturing process complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The chip is divided into distinct first device regions and second device regions, with each region optimized for specific device types. Flash memory devices are formed in first device regions while other circuit devices are formed in second device regions, allowing independent process optimization for each device type while maintaining overall integration.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different gate dielectric layer structures are implemented in different regions of the chip. The first gate dielectric layer structure with charge trapping layer is used in flash memory regions, while other gate dielectric layer structures are used in other device regions, enabling region-specific performance optimization.

Inventive Principle:

Principle #3Local quality

2Reliability

If different gate dielectric layer structures are used for flash memory and other devices, then device performance is optimized, but manufacturing process complexity increases

Engineering Contradiction:

Improvedevice performanceVSAvoidprocess simplicity

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The gate dielectric layer structure is segmented into different configurations for different device types. Flash memory devices receive a first gate dielectric layer structure with charge trapping layers, while other devices receive second gate dielectric layer structures, allowing each to be optimized for its specific function.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Charge trapping layers are formed in the gate dielectric layer structure before subsequent processing steps. This preliminary formation of charge trapping layers enables flash memory-specific functionality to be established early in the manufacturing process, facilitating later process steps.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If charge trapping layers are formed in gate dielectric layers, then charge retention capability is improved, but manufacturing precision requirements increase

Engineering Contradiction:

Improvecharge retention capabilityVSAvoidlayer formation precision

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The gate dielectric layer structure is formed as a composite structure including multiple layers such as oxide layers, nitride layers, and charge trapping layers. Each layer contributes specific properties, with the charge trapping layer providing charge storage capability while other layers provide dielectric and protective functions, collectively achieving reliable charge retention.

Inventive Principle:

Principle #40Composite materials

Solution Approach 2:

The charge trapping layer is nested within the gate dielectric layer structure, positioned between the gate electrode and the channel region. This nested configuration allows the charge trapping functionality to be integrated within the existing gate dielectric structure without requiring separate external components.

Inventive Principle:

Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables efficient charge retention and reduced threshold voltage mismatch, facilitating the integration of flash memory devices with other circuits while maintaining manufacturing cost-effectiveness.

Implementation Method 1

Flash memories, which use dielectric trapping layers or floating layers to store charges

Methodology Applied

Scientific EffectDielectric trapping: Dielectric

Implementation Method 2

forming a first high-k dielectric layer over the top dielectric layer

Methodology Applied

Scientific EffectDielectric permittivity: Dielectric Permittivity

Data Source

PatentUS9929168B2Embedded memory and methods of forming the same

Publication Date: 2018.03.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method for forming an embedded flash memory device includes a gate stack, and source and drain regions in the semiconductor substrate is disclosed. The first source and drain regions are on opposite sides of the gate stack. The gate stack includes a bottom dielectric layer over the semiconductor substrate, a charge trapping layer over the bottom dielectric layer, a top dielectric layer over the charge trapping layer, a high-k dielectric layer over the top dielectric layer, and a metal gate over the high-k dielectric layer.