Solid-State Devices TRIZ Cases

Vertical transistor stacking reduces memory cell area by four times while maintaining backend fabrication compatibility.

A display substrate bonding region uses a secondary metal pattern to cover the primary conductive layer, preventing chemical interaction during manufacturing.

An OLED electrode design using an interposed patterned conductive layer reduces impedance and prevents short circuits caused by printing roughness.

Fixed charge layers induce virtual channels in NAND memory cells, reducing short channel effects and source/drain resistance without dopant implants.

An organic transition layer with matched refractive index and energy levels reduces reflection and injection barriers to improve OLED luminous efficiency.

A monolithic ceramic luminescence converter embeds phosphors in a silicon nitride matrix to enhance color homogeneity and light-extraction efficiency.

A light shielding covering portion protects connection pads and switch elements within the display region of an organic electroluminescence panel.

An optical shielding element absorbs stray signals to prevent crosstalk between adjacent units, improving measurement accuracy.

Stacked light-emitting elements with optimized optical path lengths resolve yield issues from metal mask defects while boosting luminance.

Segmented auxiliary electrode with conductive pattern reduces electrical resistance while maintaining high transmittance for external light.

Plating a conductive liner in pad cavities boosts substrate adhesion strength without exceeding temperature limits that damage semiconductor devices.

Portable sealed unit process apparatuses enable flexible semiconductor manufacturing line reconfiguration.

Conductive layer creates band bending to electrically pin the back surface, eliminating high-temperature annealing and reducing fabrication complexity.

Electrically floating barrier region reduces switching losses while controlling voltage and current slopes.

A segmented image sensor divides pixels into distinct regions to capture light under different conditions for simultaneous focus detection and exposure calculation.

Direct contact between the bit line and data storage element reduces resistance while maintaining alignment margins for high integration density.

A mesa photodiode array uses a high-density doped region between pads to form an electrical potential barrier.

A photosensitizing chip package uses a glass substrate with weirs to define a gap over color attachment arrays.

Vertical stacking of electrostatic actuators and capacitive sensors reduces device dimensions while maintaining high optical resolution.

Reducing pixel density in the translucent display region enhances light transmittance for under-display sensors while maintaining screen-to-body ratio.

Applying switching voltage between gate and source electrodes without generating channel current prevents charge trap buildup in the high-k dielectric layer.

Metal particles reinforce the frit sealing layer to maintain structural integrity against external impacts while blocking oxygen entry.

An intermediary dielectric layer reduces stray light reflections at the wiring interface to improve optical efficiency.

Oxygen-doped sidewall layers stabilize threshold voltage by filling vacancies, preventing parasitic channels and improving reliability.

A diffraction pattern layer bonded to a pixel substrate increases the effective emission area ratio in display manufacturing.

Segmented epitaxial growth converts silicon fins to silicon germanium, preventing germanium diffusion into adjacent n-channel device regions.

Trench isolation segments SPADs to prevent optical cross-talk, preserving sensitive area without complex through-silicon vias.

Varying anode electrode opening sizes eliminates dummy regions, expanding the usable display area while maintaining manufacturing precision.

A chalcogenide glass composition with specific silicon and germanium ratios maintains stable electrical properties in switch devices.

Segmented charge carrier generation zones using mixed organic and inorganic layers maintain voltage stability at high temperatures.

Ethynylene heteroacene polymers resist oxidative doping in ambient air, eliminating costly vacuum deposition and inert atmosphere requirements.

Merging encapsulation functions into the capping layer reduces structural complexity and manufacturing steps while maintaining moisture protection.

A double trench isolation process fills deep structures with void-free dielectric material.

Buchwald-Hartwig polymerization creates high molecular weight amino dihydrophenanthrene polymers with alternating nitrogen and aromatic backbones.

A programmable interconnect matrix dynamically routes signals between functional elements to reduce silicon area and power consumption in integrated circuits.

Fused nanoparticles create a curved surface that refracts light, reducing total internal reflection at the glass-air interface.

Integrated OLED structure uses multi-plane stacking to separate blue and green-red emissive areas for optimized device performance.

Auxiliary pattern layer blocks lateral current flow between sub-pixels in organic light-emitting display panels.

A maskless exposing device projects patterns onto photoresist layers to fabricate thin film transistor substrates without physical masks.

Adjusting blue sub-pixel area reduces current density to extend color-coordinate life while maintaining peak luminance of pure colors.

A vertical non-volatile memory device uses dummy charge storage layers to insulate active data storage structures within a stacked semiconductor pillar.

Arranges transistors in gate width direction to prevent photolithography misalignment and maintain breakdown voltage.

Sliding plates position polyurethane shock absorbers between set frames to absorb external shocks before they damage the panel or internal structures.

A collimator filter layer with aligned apertures directs light onto image sensor elements to enable optical fingerprint detection.

A display device stacks overlapping panels where a lower panel features a light-transmitting region aligned with an upper panel's display area.

Inner dam and blocking element shield light-emitting stack while substrate hole placement reduces non-display bezel area.

Oxidizing a sacrificial metal layer then removing it exposes the first metal surface, reducing interface oxide formation that increases contact resistance.

A cluster system processes organic films continuously to eliminate metal mask alignment errors and impurity exposure in high-resolution displays.

Forming an interconnect within a recessed epitaxial region provides low resistance contact while reducing thermal budget and manufacturing complexity.

Stressor pillars apply vertical tensile stress to vertical semiconductor channels, enhancing charge carrier mobility despite increased channel length.

Physical vapor deposition creates a resistance variable film with distinct crystalline and amorphous regions.

Vertical trench capacitors reduce cell area while maintaining storage capacitance, eliminating the need for buried straps.

Converting amorphous silicon to crystalline silicon via a seed layer improves electrical conductivity and carrier mobility in resistive memory devices.

Sidewall thickness variation reduces junction leakage and improves memory refresh characteristics by mitigating short channel effects.

A semiconductor device integrates a transistor and capacitor using an oxide insulating film to reduce oxygen vacancies in the oxide semiconductor layer.

Relocating the metal wire array to the bending region reduces packaging width, resolving the trade-off between bezel size and connection reliability.

Polyselenophene polymers lower bandgaps and block electron leakage to boost power conversion efficiency beyond six percent.

Silicon nitride liners protect tunnel dielectrics from degradation while enabling dense dielectric filling of narrow isolation trenches.

A symmetrical lens with varying thickness redistributes light from the LED die, resolving non-uniform intensity concentration at the center.

A reference sense module creates a copy of cell currents to compensate for off-leak accumulation and secure the read margin.

Charge trapping gate stacks with high-k dielectrics resolve threshold voltage mismatch during System-On-Chip integration.

A cooling dopant converts triplet excitons to singlet excitons in the emission layer.

Distinct impurity distributions in conductive layers suppress diffusion to insulating layers, preventing depleted region expansion and improving writing speed.

Nested color filters within openings prevent mixture defects while simplifying manufacturing and reducing material usage.

Composite host materials balance charge injection to reduce driving voltage and extend device lifetime.

Segmenting the organic material into three layers with optimized HOMO energy levels resolves the trade-off between high efficiency and low driving voltage.

A display panel uses a light blocking member between color filters to maintain cell gap while leaving transistors exposed.

A vertical memory device manufacturing method forms uniform semiconductor patterns through a sacrificial layer gap.

Profiled mating surfaces join orthogonal optoelectronic members using UV-curable adhesives and conductive voids.

A SONOS memory device surrounds dielectric layers with a conformal charge trapping film to eliminate current leakage paths.

A method forms NVM cells and logic transistors using a shared low-temperature high-k gate dielectric layer.

Sliding projections crush the lead frame end to form lateral barriers that block resin gaps and prevent terminal attachment.

Slits interrupt control gates between alternating pillar rows, maintaining minimum spacing to resolve structural compactness limits in 3D semiconductor memory.

Scannable configuration registers enable unique addressing and testing of identical chips in a 3D stack using minimal I/O resources.

Laminated opaque dielectric carrier integrates optical IC chips within confined cavities, reducing manufacturing complexity and device thickness.

A display panel uses intersecting first and second metal layers to form a mesh structure that supplies signal voltage to pixel units.

Segmented heat dissipating wire conducts thermal energy away from organic light emitting diode through sealant interface to suppress degradation.

Segmenting the phosphor layer minimizes heat transfer and optical loss while maintaining consistent color temperature across viewing angles.

Near-infrared organic light-emitting diodes and photosensitive diodes integrate between display pixels to enable biometric sensing.

A foldable display panel incorporates a deformation layer with force-strained material to detect structural changes.

Merging self-capacitance electrodes with OLED anodes eliminates cathode shielding effects, boosting signal-to-noise ratio and reducing manufacturing costs.

A fingerprint identification circuit uses a partially-transparent member on an opposite substrate to transmit operational light.

A tandem organic electroluminescent apparatus uses a microcavity to enhance emission intensity.

Increasing organic layer height redistributes bending stress, preventing wiring layer breakage and improving LTPS-OLED yield.

Segmented tubular heaters reduce current requirements by shrinking the contact area between the heating element and chalcogenic material.

A metal oxide resistive switching memory structure integrates with standard CMOS flows using a W-plug lower electrode and sequential layer deposition.

Water vapor plasma treatment reduces fluorine levels by 50% and forms an aluminum oxide passivation layer to prevent discoloration.

Composite spacer with underlying metal layer maintains interval between display and sealing substrates, preventing deformation from external shocks.

Parallel ESD diodes in FinFET structures utilize alternating N+ and P+ diffusions to achieve high current sinking capability.

Segmented thickness in the resistance switching layer confines conductive paths to prevent lateral interference and stabilize operation voltage.

A semiconductor device uses insulating portions to divide drain-side selection gate electrode layers within a stacked body structure.

Segmented conductive protection layers optimize optical resonance distances in organic light emitting display devices.

A memristor circuit integrates a field effect transistor to amplify conductance change signals while preserving linearity and symmetry.

Asymmetric light shielding portions adjust pixel opening ratios to maintain constant brightness across different pixels.

Separate etching of the diode line and heating electrode prevents structural leaning, stabilizing resistance states and shortening fabrication time.

Continuous wave laser irradiation recrystallizes semiconductor films to eliminate surface ridges and reduce transistor characteristic variation.

A sense circuit determines resistive states in memory arrays using field effect transistors to control current flow.

Supplement members absorb external shocks delivered to the sealing portion, preventing structural damage and maintaining bonding strength between substrates.