Solid-State Devices TRIZ Cases

Vertical transistor stacking reduces memory cell area by four times while maintaining backend fabrication compatibility.

A display substrate bonding region uses a secondary metal pattern to cover the primary conductive layer, preventing chemical interaction during manufacturing.

An OLED electrode design using an interposed patterned conductive layer reduces impedance and prevents short circuits caused by printing roughness.

Fixed charge layers induce virtual channels in NAND memory cells, reducing short channel effects and source/drain resistance without dopant implants.

An organic transition layer with matched refractive index and energy levels reduces reflection and injection barriers to improve OLED luminous efficiency.

A monolithic ceramic luminescence converter embeds phosphors in a silicon nitride matrix to enhance color homogeneity and light-extraction efficiency.

A light shielding covering portion protects connection pads and switch elements within the display region of an organic electroluminescence panel.

An optical shielding element absorbs stray signals to prevent crosstalk between adjacent units, improving measurement accuracy.

Stacked light-emitting elements with optimized optical path lengths resolve yield issues from metal mask defects while boosting luminance.

Segmented auxiliary electrode with conductive pattern reduces electrical resistance while maintaining high transmittance for external light.

Plating a conductive liner in pad cavities boosts substrate adhesion strength without exceeding temperature limits that damage semiconductor devices.

Portable sealed unit process apparatuses enable flexible semiconductor manufacturing line reconfiguration.

Conductive layer creates band bending to electrically pin the back surface, eliminating high-temperature annealing and reducing fabrication complexity.

Electrically floating barrier region reduces switching losses while controlling voltage and current slopes.

A segmented image sensor divides pixels into distinct regions to capture light under different conditions for simultaneous focus detection and exposure calculation.

Direct contact between the bit line and data storage element reduces resistance while maintaining alignment margins for high integration density.

A mesa photodiode array uses a high-density doped region between pads to form an electrical potential barrier.

A photosensitizing chip package uses a glass substrate with weirs to define a gap over color attachment arrays.

Vertical stacking of electrostatic actuators and capacitive sensors reduces device dimensions while maintaining high optical resolution.

Reducing pixel density in the translucent display region enhances light transmittance for under-display sensors while maintaining screen-to-body ratio.

Applying switching voltage between gate and source electrodes without generating channel current prevents charge trap buildup in the high-k dielectric layer.

Metal particles reinforce the frit sealing layer to maintain structural integrity against external impacts while blocking oxygen entry.

An intermediary dielectric layer reduces stray light reflections at the wiring interface to improve optical efficiency.

Oxygen-doped sidewall layers stabilize threshold voltage by filling vacancies, preventing parasitic channels and improving reliability.

A diffraction pattern layer bonded to a pixel substrate increases the effective emission area ratio in display manufacturing.

Segmented epitaxial growth converts silicon fins to silicon germanium, preventing germanium diffusion into adjacent n-channel device regions.

Trench isolation segments SPADs to prevent optical cross-talk, preserving sensitive area without complex through-silicon vias.

Varying anode electrode opening sizes eliminates dummy regions, expanding the usable display area while maintaining manufacturing precision.

A chalcogenide glass composition with specific silicon and germanium ratios maintains stable electrical properties in switch devices.

Segmented charge carrier generation zones using mixed organic and inorganic layers maintain voltage stability at high temperatures.

Ethynylene heteroacene polymers resist oxidative doping in ambient air, eliminating costly vacuum deposition and inert atmosphere requirements.

Merging encapsulation functions into the capping layer reduces structural complexity and manufacturing steps while maintaining moisture protection.

A double trench isolation process fills deep structures with void-free dielectric material.

Buchwald-Hartwig polymerization creates high molecular weight amino dihydrophenanthrene polymers with alternating nitrogen and aromatic backbones.

A programmable interconnect matrix dynamically routes signals between functional elements to reduce silicon area and power consumption in integrated circuits.

Fused nanoparticles create a curved surface that refracts light, reducing total internal reflection at the glass-air interface.

Integrated OLED structure uses multi-plane stacking to separate blue and green-red emissive areas for optimized device performance.

Auxiliary pattern layer blocks lateral current flow between sub-pixels in organic light-emitting display panels.

A maskless exposing device projects patterns onto photoresist layers to fabricate thin film transistor substrates without physical masks.

Adjusting blue sub-pixel area reduces current density to extend color-coordinate life while maintaining peak luminance of pure colors.

A vertical non-volatile memory device uses dummy charge storage layers to insulate active data storage structures within a stacked semiconductor pillar.

Arranges transistors in gate width direction to prevent photolithography misalignment and maintain breakdown voltage.

Sliding plates position polyurethane shock absorbers between set frames to absorb external shocks before they damage the panel or internal structures.

A collimator filter layer with aligned apertures directs light onto image sensor elements to enable optical fingerprint detection.

A display device stacks overlapping panels where a lower panel features a light-transmitting region aligned with an upper panel's display area.

Inner dam and blocking element shield light-emitting stack while substrate hole placement reduces non-display bezel area.

Oxidizing a sacrificial metal layer then removing it exposes the first metal surface, reducing interface oxide formation that increases contact resistance.

A cluster system processes organic films continuously to eliminate metal mask alignment errors and impurity exposure in high-resolution displays.

Forming an interconnect within a recessed epitaxial region provides low resistance contact while reducing thermal budget and manufacturing complexity.