1S-1T Ferroelectric Memory Cell Area Reduction
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Solution Overview
Problem
Conventional eDRAM and eSRAM technologies consume significant area due to transistor pitch limitations, necessitating compact memory structures that can leverage suitable physical properties for area conservation.
Innovation Solution
The development of a 1S-1T compact ferroelectric memory cell (CFMC) utilizing a ferroelectric gate vertical transistor (FGVT) and a selector device, which employs a ferroelectric material to establish persistent built-in voltage and charge, modulating the threshold voltage and conductivity between the source and drain regions, allowing for a non-disturbing read and reducing area by 4x compared to state-of-the-art devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional eDRAM and eSRAM structures are used, then memory functionality is achieved, but area consumption is excessive due to transistor pitch limitations
Solution Approach 1:
The patent transitions from planar transistor configurations to vertical transistor structures, utilizing the third dimension (vertical stacking) to reduce the footprint area. The vertical transistor architecture allows memory cells to be stacked vertically rather than arranged in a planar grid, thereby achieving 4x area reduction while maintaining functionality.
Solution Approach 2:
The patent changes the physical configuration parameter of the transistor from horizontal/planar arrangement to vertical stacking. This parameter change enables denser integration by exploiting the vertical dimension, directly addressing the area consumption problem caused by conventional transistor pitch limitations.
2Area of stationary object
If ferroelectric materials are used to reduce area, then compact memory structures are achieved, but fabrication complexity increases
Solution Approach 1:
The patent merges the ferroelectric capacitor and transistor functions into an integrated vertical structure where the ferroelectric layer is incorporated within the vertical transistor stack. This merging approach allows area reduction through compact integration while managing fabrication complexity by combining multiple functions into a unified structure that can be processed in fewer steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 1S-1T CFMC achieves a 4x reduction in area while maintaining efficient backend transistor fabrication and array efficiency, enabling compact memory structures with persistent built-in voltage and charge, facilitating effective threshold voltage modulation and conductivity control.
Implementation Method 1
Ferroelectricity is a property of certain materials that have a spontaneous electric polarization that can be reversed by the application of an external electric field
Implementation Method 2
Ferroelectric materials exhibit a hysteresis effect, which allows for switching between two polarized states
Implementation Method 3
If the ferroelectric is coupled to a semiconductor such as a FET, changing the gate capacitance will cause a change in the conductivity between the source and drain of the semiconductor (channel)
Data Source
AI summary
A 1S-1T ferroelectric memory cell is provided that include a transistor and a two-terminal selector device. The transistor exhibits a low conductive state and a high conductive state (channel resistance), depending on drive voltage. The two-terminal selector device exhibits one of an ON-state and an OFF-state depending upon whether the transistor is in its low conductive state or its high conductive state. The transistor may be, for instance, a ferroelectric gate vertical transistor. Modulation of a polarization state of ferroelectric material of the vertical transistor may be utilized to switch the state of the selector device. The memory cell may thus selectively be operated in one of an ON-state and an OFF-state depending upon whether the selector device is in its ON-state or OFF-state.