Semiconductor Memory Select Transistor Drain Region Connection
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Solution Overview
Problem
The reliability of semiconductor devices with MONOS type memory transistors and select transistors arranged side by side in the gate length direction is compromised due to misalignment in photolithography processes, leading to reduced breakdown voltage and potential deterioration in device performance.
Innovation Solution
The semiconductor device design includes separate regions for select transistors and memory transistors, with electrical connections made via wirings, allowing for increased pattern sizes and distances, thereby preventing misalignment issues and maintaining high breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the memory transistor and the select transistor are arranged side by side in the gate length direction, then the device area is reduced, but the breakdown voltage is remarkably lowered due to misalignment between device dimension and photolithography process
Solution Approach 1:
The patent changes the arrangement direction from the gate length direction (horizontal arrangement) to the gate width direction (vertical arrangement). This dimensional change allows the transistors to be stacked rather than placed side-by-side, eliminating the misalignment issue between photolithography processes while maintaining compact area utilization through vertical integration.
2Area of stationary object
If the memory transistor and the select transistor are arranged side by side in the gate length direction, then the device area is reduced, but the manufacturing precision is compromised due to photolithography misalignment
Solution Approach 1:
The patent transitions from horizontal arrangement (gate length direction) to vertical arrangement (gate width direction), stacking transistors in the vertical dimension. This eliminates sensitivity to photolithography misalignment in the horizontal plane, as the vertical stacking uses different process steps that are not affected by the same alignment errors.
3Adaptability or versatility
If separate gate dielectric films are formed for memory transistor and select transistor, then the transistors can be independently optimized, but the breakdown voltage decreases due to misalignment
Solution Approach 1:
By arranging transistors in the gate width direction rather than gate length direction, the patent enables separate gate dielectric film formation for each transistor type while preventing misalignment issues. The vertical stacking allows independent processing steps for each transistor's gate dielectric without the horizontal alignment constraints that would compromise breakdown voltage.
Data Source
AI summary
A plurality of select transistors are formed in a first region of a semiconductor substrate, a plurality of memory transistors are formed in a second region of the semiconductor substrate, and a drain region of the select transistor and a source region of the memory transistor are electrically connected to form a memory cell. Here, the first region and the second region are arranged with each other in a gate width direction of the select transistor and the memory transistor.