Strata Manager for 3D IC Stack Configuration
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Solution Overview
Problem
In 3D stacked integrated circuits, existing methods require a large number of I/Os and TSVs to test and configure individual strata, which is inefficient and costly, especially when stacking multiple strata with physically identical chips that need unique address assignments and clock sources.
Innovation Solution
A strata manager with scannable configuration registers and stratum identification circuits allows for programming and identification of individual strata using a small number of I/O and TSV positions, enabling efficient test and configuration of strata within the stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate stack I/Os and inclined TSVs are provided for each stratum to enable individual testing and configuration, then each stratum can be tested and configured independently, but the number of I/Os and TSVs increases significantly
Solution Approach 1:
The patent merges the configuration and identification functions into a unified scannable register structure that can be accessed through a small number of shared I/Os. Multiple strata share common configuration resources rather than having dedicated I/Os per stratum, reducing overall complexity while maintaining individual configurability.
Solution Approach 2:
The configuration registers are designed to serve multiple functions: they provide both identification information and operational configuration for each stratum. The same register structure is used across all strata, allowing a universal interface to manage diverse stratum types and configurations without requiring stratum-specific I/Os.
2Ease of manufacture
If physically identical chips are used in the stack to reduce cost, then manufacturing cost decreases, but unique address assignment and functional differentiation become challenging
Solution Approach 1:
The patent introduces local quality by providing each stratum with unique identification bits and configuration capabilities within the identical physical structure. While all chips are manufactured the same way, the scannable registers contain stratum-specific information (such as position identifiers) that enable functional differentiation and unique addressing without requiring physical variations.
Solution Approach 2:
The configuration registers are pre-loaded with stratum identification information during or before stacking. This preliminary assignment of unique identifiers allows the system to differentiate between identical physical chips and assign appropriate functions based on their position or designated role in the stack, all before the actual operational configuration takes place.
3Device complexity
If a small number of I/Os and TSVs are used for stratum configuration, then resource usage is reduced, but the ability to test and configure individual strata becomes limited
Solution Approach 1:
The patent resolves the I/O bottleneck by moving from a spatial dimension solution (more physical I/Os) to a temporal dimension solution (scanning through configuration registers over time). Instead of providing simultaneous access to each stratum through dedicated I/Os, the system uses sequential scanning of configuration registers, allowing individual stratum access through time-multiplexed use of shared I/O resources.
Solution Approach 2:
The scannable configuration registers act as an intermediary between the limited external I/Os and the individual strata. These registers buffer and manage the configuration data, allowing a small number of I/Os to effectively communicate with and configure multiple strata by sequentially loading and reading configuration information through the register chain.
Data Source
AI summary
There is provided a strata manager within a 3D chip stack having two or more strata. The strata manager includes a plurality of scannable configuration registers, each being arranged on a respective one of the two or more strata for storing a set of bits. The set of bits is configured to program an operation of a corresponding one of the two or more strata on which the set of bits is stored or a device thereon. Additionally, a stratum identifier within a 3D stack and stack-wide scan circuit within a 3D stack are provided.