NVM and Logic Integration via Low-Temperature High-k Gate Dielectrics
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuits with both non-volatile memory (NVM) and logic functions face challenges in achieving high performance without sacrificing logic performance or increasing costs.
Innovation Solution
The method involves contemporaneously forming NVM cells with high-k gate dielectrics and metal gates, using metal nanocrystals as charge storage, and carefully managing metal layers to create both N-channel and P-channel transistors, allowing for efficient integration without high-temperature processing that could damage high-k materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional processing steps are added to achieve high performance for both logic and NVM, then performance is improved, but manufacturing cost and complexity increase
Solution Approach 1:
The patent merges the formation of high-k dielectric layers for both logic and NVM regions into a single low-temperature ALD process step. This combining of operations achieves high performance for both transistor types without proportionally increasing process complexity, as the same equipment and material deposition techniques are used for both regions.
Solution Approach 2:
The high-k dielectric layer serves multiple functions: it acts as the gate dielectric for logic transistors and as the tunnel oxide for NVM cells. This multi-functionality eliminates the need for separate dielectric layers for each device type, reducing overall process complexity while maintaining high performance for both logic and NVM operations.
2Ease of manufacture
If conventional processing temperatures are used, then manufacturing is simpler, but high-k materials are damaged and NVM performance suffers
Solution Approach 1:
The patent changes the temperature parameter from conventional high-temperature processing (>400°C) to low-temperature processing (<400°C) for high-k dielectric formation. This parameter change preserves high-k material integrity while maintaining manufacturing feasibility through the use of ALD, which can effectively deposit high-k materials at lower temperatures with appropriate process optimization.
Data Source
AI summary
A method includes forming a gate dielectric over a substrate in an NVM region and a logic region; forming a first conductive layer over the gate dielectric in the NVM region and the logic region; patterning the first conductive layer in the NVM region to form a select gate; forming a charge storage layer over the select gate in the NVM region and the first conductive layer in the logic region; forming a second conductive layer over the charge storage layer in the NVM region and the logic region; removing the second conductive layer and the charge storage layer from the logic region; patterning the first conductive layer in the logic region to form a first logic gate; and after forming the first logic gate, patterning the second conductive layer in the NVM region to form a control gate which overlaps a sidewall of the select gate.