U-Shaped Memory Cell Strings for 3D NAND Storage Density

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Solution Overview

Problem

Existing 3D semiconductor memory architectures face limitations in structural compactness due to the need for interruptions in the regularity of memory cell arrays to define bit line selectors, source line selectors, and control gates, which hampers data storage capacity per unit area.

Innovation Solution

A 3D memory device with U-shaped memory cell strings, where bit line and source line selectors are arranged with slits that interrupt the control gates, allowing for a more compact structure by maintaining the minimum distance between rows of pillars, thus increasing storage capacity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If traditional 2D memory architecture is used, then manufacturing is simpler, but storage capacity per unit area is limited

Engineering Contradiction:
Improvestorage capacity per unit areaVSAvoidmemory architecture complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent transitions from traditional 2D planar memory architecture to a 3D vertical architecture by stacking multiple memory cell layers above the substrate. This dimensional change allows memory cells to be arranged in three-dimensional space, significantly increasing the storage capacity per unit area while managing the complexity through systematic layer stacking

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of operation

If interruptions are introduced to define bit line selectors and source line selectors, then selective access is enabled, but structural compactness is reduced

Engineering Contradiction:
Improveselective access capabilityVSAvoidstructural compactness
Core Design Contradiction:
Ease of operationVSArea of stationary object

Solution Approach 1:

The patent segments the memory structure by introducing slits that divide the control gates into distinct bit line selector and source line selector portions. These slits create separated regions that enable independent control of bit lines and source lines, facilitating selective access to memory cells while maintaining overall structural compactness through the integrated 3D arrangement

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10510768B23D memory device with U-shaped memory cell strings
Publication Date: 2019.12.17 AVANEIDI SPA
  • US10510768B2 patent drawing
  • US10510768B2 patent drawing
  • US10510768B2 patent drawing

AI summary

A 3D memory device comprises: a substrate; a plurality of U-shaped memory cells strings each including a first, bit line-side string portion or pillar, a second, source line-side string portion or pillar and a buried string portion formed in the substrate and connected to a first end of the first string portion and to a first end of the second string portion, the U-shaped memory cells strings including stacks of memory cells along the first and second string portions. Bit line selectors are arranged at a second end of the first string portions opposed to the first end, for the selective connection to respective bit lines; source line selectors are arranged at a second end of the second string portions opposed to the first end, for the selective connection to respective source lines. There are first groups of first string portions, wherein in each first group the first string portions are aligned along a first direction to form a respective first row of first string portions; there are second groups of second string portions, wherein in each second group the second string portions are aligned along the first direction to form a respective second row of second string portions. The first rows of first string portions and the second rows of second string portions follow one another, alternately or in pairs, along a second direction transversal to the first direction. First rows of first string portions and/or second rows of second string portions consecutive along said second direction are spaced apart from each other a respective distance. Between a first row of first string portions and a second row of second string portions being consecutive along the second direction and spaced apart a distance equal to or less than a minimum distance allowed by the resolution of the manufacturing technology a respective slit is formed that extends in a third direction, orthogonal to the first and second directions, from the second end down to the substrate, the slit, interrupting layers forming the bit line selectors and the source line selectors and control gates of the memory cells of the memory cells stacks, with dimension, along the second direction, less than, equal to or higher than the minimum distance, and walls of the slit lying in planes parallel to the first and third directions delimit the first and second string portions.